Specifications

CDS Carrier Architecture
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor 3-7
3.3.2.4 LED Data Register
The LED data register can be used to directly control the LED monitoring outputs, when
CM_XCSR[LED] is set to one.
3.3.2.5 PCI Control/Status Register
The PCI control/status register monitors and controls the PCI environment.
6 HRESET This bit allows a device to assert HRESET to itself. As HRESET may be a level-sensitive signal
(device-dependent), it is a self-resetting bit.
7 SRESET This bit allows a device to assert SRESET to itself. As SRESET may be a level-sensitive signal
(device-dependent), it is a self-resetting bit.
01234567
RLED
W
Reset00000000
Offset 0x05
Figure 3-6. Reset Control Register (CM_LED)
Table 3-6. CM_LED Field Descriptions
Bits Name Description
0–7 LED Corresponding values for CDC monitoring LEDs L0–L7. Setting a bit to one illuminates the LED.
01234567
R M66O PCIXCO M66S DUAL PSPEED PCIX PCIEN
W0 0
Reset00000000
Offset 0x06
Figure 3-7. PCI Control/Status Register (CM_PCI)
Table 3-5. CM_RST Field Descriptions (continued)
Bits Name Description