Specifications

MPC8555E Configurable Development System Reference Manual, Rev. 1
iv Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
3.3.2.3 Reset Control Register (CM_RST).......................................................................... 3-6
3.3.2.4 LED Data Register................................................................................................... 3-7
3.3.2.5 PCI Control/Status Register..................................................................................... 3-7
3.3.2.6 DMA Control Register ............................................................................................ 3-8
3.4 CPM Connections............................................................................................................ 3-9
3.5 ATM Interfaces .............................................................................................................. 3-12
3.6 Ethernet Ports................................................................................................................. 3-12
3.7 Local Bus ....................................................................................................................... 3-15
3.7.1 NCDS Local Bus Signals........................................................................................... 3-17
3.8 Clock.............................................................................................................................. 3-18
3.9 PCI-X............................................................................................................................. 3-19
3.9.1 PCI Arbitration .......................................................................................................... 3-20
3.9.2 PCI-X System Control............................................................................................... 3-21
3.10 Exceptions...................................................................................................................... 3-21
3.10.1 Software Triggered Exceptions.................................................................................. 3-23
3.11 Reset............................................................................................................................... 3-23
3.11.1 Software Triggered Resets......................................................................................... 3-24
3.12 I2C ................................................................................................................................. 3-25
3.13 Configuration................................................................................................................. 3-26
3.14 Power ............................................................................................................................. 3-28
3.14.1 +2.5-V Power............................................................................................................. 3-29
3.14.2 Power Management ................................................................................................... 3-29
3.15 Diagnostic Features........................................................................................................ 3-29
3.15.1 Analyzer Headers....................................................................................................... 3-29
3.15.2 Remote Debug Header............................................................................................... 3-33
3.15.3 Monitoring LEDs....................................................................................................... 3-33
Chapter 4
CDS Daughtercard Architecture
4.1 Mechanical Architecture.................................................................................................. 4-1
4.2 CDS Daughtercard (CDC) Block Diagram ..................................................................... 4-4
4.3 Processor.......................................................................................................................... 4-4
4.4 DDR Memory .................................................................................................................. 4-4
4.4.1 DDR Interface Termination ......................................................................................... 4-7
4.4.2 Recommended Part Numbers ...................................................................................... 4-8
4.5 Local Bus Interface..........................................................................................................4-8
4.5.1 Local Bus SDRAM Memory..................................................................................... 4-10
4.6 Passive Connections ...................................................................................................... 4-10
4.7 Carrier Pinouts ............................................................................................................... 4-12
4.8 Clock.............................................................................................................................. 4-12