Specifications

Quick Start-Up Guide
MPC8555E Configurable Development System Reference Manual, Rev. 1
2-10 Freescale Semiconductor
b
4 1 Local clock R(2:1) 1 10 Part of 33 MHz SYSCLK
20
3 Local clock V(6:1) 0 001000 Part of 33 MHz SYSCLK
40
51
60
70
80
Notes:
1. SW1(3) for Configuration 2 is PCI CLK SEL and must be set to 1.
2. SW2(6) for Configuration 2 is PCI Select PCI = 1 and PCIX = 0.
Table 2-3. Default Status of Arcadia Board Switches (Arcadia C3.n)
SW Bit Name
Default
(1 = ON)
Note
1 1 TSI310: BAR_EN 0 0 BAR0 disabled
1 BAR0 enabled
2 Secondary bus internal arbiter enable
TSI310: S_INT_ARB_EN
0 0 Use internal arbiter
1 Use external arbiter
3 Physical width of the PCI-X device
TSI310: 64_BIT_DEVICE
0 0 Bridge is a 64-bit bus
1 Bridge is a 32-bit bus
4 Opaque region enable
TSI310: OPAQUE_EN
0 0 Opaque memory enable
1 Opaque memory enable
5 Secondary PCI IDSEL remap
TSI310: IDSEL_REROUTE_EN
0 0 IDSEL remap mask is 0000_0000
1 IDSEL remap mask is 22F2_0000
6 Secondary high-speed rate select
TSI310: S_SEL100
1 0 PCI-X highest speed is 133 MHz
1 PCI-X highest speed is 100 MHz
7 Primary configuration busy
TSI310: P_CFG_BUSY
0 0 Primary side responds to configuration cycles
normally
1 Primary side configuration cycles are retried until
bit 2 of the miscellaneous control registers is set
to 0 by a secondary configuration cycle write
8 Primary driver mode control
TSI310: P_DRVR_MODE
0 0 Normal impedance
1 Lower impedance for heavier loads
Table 2-2. Default Status of Carrier Board Switches (Configuration 1) (continued)
SW Bit Name
Default
(1 = ON)
Note