Specifications

Arcadia Motherboard Architecture
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor 5-21
5.11 Configuration
Arcadia contains several slide-switches used to configure the board, processors(s) and chipsets for the
options shown in Table 5-14. Underlined entries are the defaults, as shipped. Since the switches operate
by connecting a pulled-up signal to ground, setting a switch to ON is indicated as ‘1’ in the table.
All switches are oriented so that ON = 1 = UP, where UP means toward the PCI and I/O connector back
panel of the ATX chassis. If the chassis is standing up with the cover off, an alternate interpretation is
ON = 1 = LEFT.
Table 5-14. Arcadia Configuration Switches
Switch No. Option Description
Default
Setting
Notes
SW1 1 TSI310: BAR_EN Default 1MB BAR enable
0/OFF: BAR0 disabled by default
1/ON: BAR0 enabled by default
0
2 TSI310: S_INT_ARB_EN Secondary bus internal arbiter enable
0/OFF: Use internal arbiter
1/ON: Use external arbiter
0
3 TSI310: 64_BIT_DEVICE Physical width of the PCI-X device
0/OFF: Bridge is a 64-bit bus
1/ON: Bridge is a 32-bit bus
0
4 TSI310: OPAQUE_EN Opaque region enable
0/OFF: Opaque memory enable = 0
1/ON: Opaque memory enable = 1
0
5 TSI310:
IDSEL_REROUTE_EN
Secondary PCI IDSEL remap
0/OFF: IDSEL remap mask is 0000_0000
1/ON: IDSEL remap mask is 22F2_0000
0
6 TSI310: S_SEL100 Secondary high-speed rate select
0/OFF: PCI-X highest speed is 133 MHz
1/ON: PCI-X highest speed is 100 MHz
1
7 TSI310: P_CFG_BUSY Primary configuration busy
0/OFF: Primary side responds to configuration
cycles normally.
1/ON: Primary side configuration cycles are
retried until bit 2 of the miscellaneous
control registers is set to 0 by a
secondary configuration cycle write.
0
8 TSI310: P_DRVR_MODE Primary Driver mode control
0/OFF:Normal impedance
1/ON:Lower impedance for heavier loads
0