Specifications

Arcadia Motherboard Architecture
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor 5-13
NOTE
As the VIA PIPC is located behind a PCI-to-PCI bridge, interrupt
acknowledge cycles cannot be used (such cycles are not forwarded across a
bridge). Interrupt servicing routines for the VIA must identify interrupting
resources (the 8259 core in the VIA) directly.
5.5.5 PCI Interrupt Bridge
Arcadia includes an optional switch to connect/disconnect the PCI domain interrupt pins. Connecting them
via the PCI_INT_BRIDGE* switch (see Section 5.11, “Configuration”) allows interrupts to be asserted
and handled on either side. Opening the bridge maintains each domain as a separate (independent) entity.
NOTE
Per the PCI bridge specification, PCI bridges such as the Tsi310 do not
forward interrupt acknowledge cycles. Thus, interrupt handlers attempting
to span the bridge will need to poll and/or handle interrupt clearing via
software.
5.5.6 PCI Configuration
Each PCI device accessible as a target has an associated bus and device number. PCI device numbers are
not globally unique, and must include the bus number. Bus 1 is the main PCI/PCI-X bus (primary), while
bus 2 is the secondary, 33-MHz (nominal) PCI bus.
Although the PCI-to-PCI bridge is nominally transparent, allowing data to flow in either direction, PCI
configuration cycles are one exception: only the primary PCI bus interface of the bridge converts type1
configuration cycles to type0 configuration cycles. Consequently, the high-speed PCI-X bridge (connected
to the HIP/CDS slots) is the PCI bridge primary connection, allowing those cards to configure the
Slot #7 INTA# PCIB4_INT3 PrPMC_INTD# | VIA_INTD# | | Slot6 INTB# | Slot7 INTA#
INTB# PCIB4_INT0 PrPMC_INTA# | VIA_INTA# | ARC_INTA# | Slot6 INTC# | Slot7 INTB#
INTC# PCIB4_INT1 PrPMC_INTB# | VIA_INTB# | ARC_INTB# | Slot6 INTD# | Slot7 INTC#
INTD# PCIB4_INT2 PrPMC_INTC# | VIA_INTC# | | Slot6 INTA# | Slot7 INTD#
ARC INTA# PCIB3_INT0 PrPMC_INTA# | VIA_INTA# | ARC_INTA# | Slot6 INTA# | Slot7 INTB# 1
INTB# PCIB3_INT1 PrPMC_INTB# | VIA_INTB# | ARC_INTB# | Slot6 INTD# | Slot7 INTC#
Notes:
1. Note that the SIOINT signal from the VIA is converted to PCI levels and shared with other PCI devices onto PCIB3_INT
bus signal 0 or 1 (software selectable).
2. Note that slots 2, 4, and 5 (the HIP/CDS slots) have paralleling interrupts in order to allow easier peer-interrupt
management (i.e., the CDS cards do not need to know what slot it is in to source interrupt assignments).
Table 5-7. Arcadia 3.1 Interrupt Assignments (continued)
Device
PCI INT
Pin
CDS
Interrupt
Bus
Attached Devices by Connection Notes