Specifications

Arcadia Motherboard Architecture
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor 5-11
Figure 5-4. Arcadia PCI Interrupts Domains
To allow the PrPMC to service interrupts from PCI1, or HIP cards to service interrupts from the PrPMC,
Southbridge, or Ethernet, the system logic contains interrupt steering logic to allow interrupts to be
replicated in one direction or the other (depending on where the host is placed).
NOTE
As the PMC slot is typically occupied by a control-plane Freescale PrPMC,
the standard software from Freescale and many legacy board support
packages reflect this viewpoint in software initialization sequences. For a
shared co-processing environment, a more complicated interrupt allocation
software will be required.
The slot interrupts are assigned in a conventional rotating pattern, where the INTA output of each card is
assigned to successive portions of the common INT
(0:3) bus, respectively.
Clock
Pwr HMZD
PrPMC
Slot 7 Slot 6 Slot 5 Slot 4 Slot 3 Slot 2
HIPSlot 2 HIPSlot 1
ARC
and PCIBoot
HMZD Pwr
PCI4
PCI3
Omni
Omni
LVDS
0–3 GHz
40-Bit
PCI/PCIX
5 V
33 MHz
32-Bit
PCI/PCIX
3 V
33–66 MHz
64-Bit
PCI
3 V
33 MHz
32-Bit
PCI4 PCI3 PCI1
PCI-X/
PCI
Bridge
PCI A
Int.
Bridge
Shifter
IDE/USB
I/O
System
RealTek
Ethernet
PCI1
System Control