User's Manual

802.11g Wireless LAN+BT SiP combo Module V2.2
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Preliminary release for evaluation, Subject to be changed without Notice
34 D08 HD8 Data Input/Output line constitute a bi-directional
bus. HD[15:0] are used to access the MODULE
MAC Host Interface register
IO, PD, 5VT, 4mA
35 -STSCHG HSTSCHG_B STATUS CHANGE indication to the host. This
signal gets active when one of the bits in the PRR
or CSR registers are set
Output, 4mA
36 -SPKR PCM_Sync Reserved for BT portion , keep its open on host
side if no use.
37 -REG HREG_B ATTRIBUTE MEMORY SELECT is driven by the
host system and is used to access the Attribute
Memory
Input, PU, 5VT
38 -INPACK HINPACK_B INPUT ACKNOWLEDGE is driven by MAC. Is
asserted when the device is selected and the
device is responding to an I/O Read command.
Output, 2mA
39 -WAIT HWAIT_B HWAIT_B is driven by MAC and allows for
extending the memory or I/O cycle
Output, 4mA
40 RESET HRESET Used to asynchronously reset the complete Module Input, PU,5VT
41 -VS2 VS2_B Voltage sense signal Output , 5VT 4mA
42 N/A WLAN_LED_B WLAN LED control signal, driven the LED
indicating the link status of WLAN
Output, 4mA
43 N/A PCM_OUT Reserved for BT portion , keep its open on host
side if no use.
44 IREQ IREQ_B INTERRUPT REQUEST to the host. In Memory
mode this pin signifies RDY/BSY_typically used
during card initialization immediately after reset or
power on. Indicates to the host that the device is
not able to transfer data
Output, 4mA
45 -WE HWE_B WRITE ENABLE is driven by the host during a
memory Write Access
Input, PU,5VT
46 -IOWR HIOWR_B I/O Write Strobe is driven by the host and is
asserted when the host wants to write to an on-chip
I/O register
Input, PU,5VT
47 -IORD HIORD_B I/O Read Strobe is driven by the host and is
asserted when the host wants to read from an on-
chip I/O register
Input, PU,5VT
48 -VS1 -VS1 Reserved Output , 5VT
49 -CE2 HCE2_B CARD ENABLE2 is driven by the host system and
is used as select strobe in both I/O and memory
mode. Enables odd numbered address bytes
Input, PU,5VT
50 D15 HD15 Data Input/Output line constitute a bi-directional
bus. HD[15:0] are used to access the MODULE
MAC Host Interface register
IO, PD, 5VT, 4mA
51 D14 HD14 Data Input/Output line constitute a bi-directional
bus. HD[15:0] are used to access the MODULE
MAC Host Interface register
IO, PD, 5VT, 4mA
52 D13 HD13 Data Input/Output line constitute a bi-directional
bus. HD[15:0] are used to access the MODULE
MAC Host Interface register
IO, PD, 5VT, 4mA
53 D12 HD12 Data Input/Output line constitute a bi-directional
bus. HD[15:0] are used to access the MODULE
MAC Host Interface register
IO, PD, 5VT, 4mA