User Manual

MiniStation All-in-One Petit Board User’s Manual
Award BIOS Setup
54
z Expansion (Full Screen)
This option allows you to enlarge application screens to full screen scale onto your display. However this option
is not inversely compatible, rendering no change when applications screens have resolutions larger than the
display resolution. The available options are Enabled and Disabled.
z Display Type at POST/BOOT
This item configures the viewing area for the POST sequence. When configured to the incorrect display setting or
Both, it blankets the POST sequence from being viewed. If you select Default, this option is useless and follows
the VGA BIOS settings. The available options are Default, LCD/CRT, LCD Only, LCD/Both, Both, CRT Only,
CRT/LCD, and CRT/Both.
5.7 Chipset Features Setup Menu
Since the features in this section are related to the chipset on the CPU board and are completely optimized,
you are not recommended to change the default settings in this setup table unless you are well oriented
with the chipset features.
ROM PCI/ISA BIOS (2A69KA5C)
CHIPSET FEATURES SETUP
AWARD SOFTWARE INC.
SDRAM RAS-to-CAS Delay : 3 CPU Warning
Temperature
: Disabled
SDRAM RAS Precharge Time : 3 Current System Temp. :
SDRAM CAS latency Time : 3 Current CPU
Temperature
:
SDRAM Precharge Control : Disabled Current CPUFAN1 Speed :
DRAM Data Integrity Mode : Non-ECC Current CPUFAN2 Speed :
System BIOS Cacheable : Disabled Vcore: VTTP :
Video BIOS Cacheable : Disabled VCC3 : +5 V :
Video RAM Cacheable : Disabled +12 V : -12 V :
8 Bit I/O Recovery Time : 3
16 Bit I/O Recovery Time : 2
Memory Hole at 15M-16M : Disabled
Passive Release : Enabled
Delayed Transaction : Disabled
AGP Aperture Size (MB) : 4 ESC : Quit ↑ ↓ → ← : Select Item
F1 : Help
PU/PD/+/-
: Modify
F5 : Old Values
(Shift)
F2 : Color
F6 : Load BIOS Defaults
F7 : Load Setup Defaults
z SDRAM RAS-to-CAS Delay
You can select RAS-to-CAS delay in HCLKs of 2 or 3. The board designer should set the values in this field,
depending on the DRAM installed. Do not change the values in this field unless you change specifications of the
installed DRAM or the installed CPU.
z SDRAM RAS Precharge Time
When synchronous DRAM is installed, the number of clock cycles of RAS precharge time depends on the DRAM
timing. Do not reset this field from the default value specified by the system designer. The available choices are 2
and 3.
z SDRAM CAS latency Time
You can select CAS latency time in HCLKs 2, 3, or Auto. The board designer should set the values in this field,
depending on the DRAM installed. Do not change the values in this field unless you change specifications of the
installed DRAM or the installed CPU.
z DRAM Data Integrity Mode
This option sets the data itegrity mode of the DRAM installed in the system. The default setting is “Non-ECC”.