User's Manual

page 8/35
Note d’étude / Technical document : URD1– OTL 5665.1– 002 / 70 884 Edition 03
Document Sagem Communications Reproduction et divulgation interdites
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2. BLOCK DIAGRAM
PA +Switch
850 / 900 /1800 /1900
(18 00MHz )
(1 900 MHz )
RFIL
RFIH
RFOL
RFOH
FE _CTRL
Ramp _ DAC
RF Subsystem
DCXO
26 MHz
Antenna
pad
EMC Subsystem
External Memory
ADDR
[22 :1 ]
DATA [15 : 0]
NCS _ RAM
NCS _ Flash
NUB
NLB
NOE
NWE
RTC
32 .768 KHz
ADC SPI
VBAT T
TMS / RTCK / TCK / NTRST / TDI / TDO / TEST / TEST1 / TEST2
Audio
Subsystem
GPIO SIM PWM
P
P P
P
E
E E
E
R
R R
R
I
I I
I
P
P P
P
H
H H
H
E
E E
E
R
R R
R
A
A A
A
L
L L
L
S
S S
S
SIM _DATA / SIM _ CLK / SIM _RST / VSIM
PWM [0:2]
UART
RXD / RTS / CTS / TXD / DCD / DTR / DSR / RI
In Out
SPI _ CLK / SPI _ IRQ / S PI _ OUT / SPI _ IN /
SPI _SEL
INTMIC _BIAS
INTMIC _P
HSET _ OUT _P
HSET _OUT _N
3 Pads
8 Pads
3 Pads
4 Pads
5 Pads
1 Pad
GROUND
3
Pads
3 +2
Pads
JTAG
9 Pads
AUX _ADC 0
VB
A
CK
UP
Power Supply System
V
G
PIO
POWER
CONTROL
1 Pad
1 Pad
1 Pad
POK _ IN
VGPIO
VBACKUP
Band 1
Band 2
Dual Saw Filter (1800 /1900 )
Band 1
Band 2
Dual Saw Filter (850 /900 )
(850 MHz )
(900 MHz )
GPIO [ 1:5]
5
Pads
1 Pad
RESET
R
E
S
E
T
Figure 1: Block diagram of HiloNC module