User's Manual

URD1 – OTL 5696.1– 022 / 72740 Edition 0.4 HILONC- 3GPS APPLICATION NOTE
each capacitor directly to the main ground plane, with one via in the capacitor’s pad plus several vias within the
surface layer ground fill area.
8.1.3. Digital ground
Digital ground should connect directly to the main ground plane. In addition, each layer between layer 1 and the
main ground should include ground fills directly below the center grid area’s digital pins, with each stack of vias
connecting to each ground fill area. The large mass of copper tied together using this technique provides
optimal electrical grounding and thermal conductivity.
8.1.4. Analog/RF ground
The analog/RF ground pins are connected to each other, but isolated from the digital ground (until main ground).
Like the digital pins, the analog/RF pins should connect directly to the main ground plane. In addition, each layer
between layer 1 and the
main ground should include ground fills directly below the outer layer’s analog/RF pins,
with each stack of vias connecting to each ground fill area. The large mass of copper tied together using this
technique provides optimal electrical grounding and thermal conductivity.
8.1.5. Power supply

A layer for power supply signals (
VBAT
,
VGPIO
) is recommended.
Looping of power signal layouts must be avoided in device design.
Ensure suitable power supply (
VBAT
,
VGPIO
) track width and thickness.
8.1.6. Clocks
Clock signals must be shielded between two ground layers and bordered with ground vias.
8.1.7. Data bus and other signals
 Data bus and commands have to be routed on the same layer. Lines of the bus should not be parallel to
other lines.
 Line crossings should be perpendicular.
Other signals should have suitable track width and thickness.
Data bus must be protected by upper and lower ground planes
8.1.8. Radio
 Provide a 50 Ohm micro strip line for antenna connection.
8.1.9. Shielding
The following shielding comments are provided for designer consideration:
At the very least the following devices and circuits should be shielded:
·
High-speed memory
·
RF front-end components
·
Crystal circuits
·
DC/DC circuits
·
RF circuitry
Recommended shield partitioning:
·
For RF matching components do not locate matching inductors too close to shield walls (this may cause
electromagnetic coupling and inductor de-Q).
·
Memory devices must be shielded.
·
Crystal circuits (other than reference circuits for RF frequency synthesizers) must be very close to their
Note d’étude / Technical document :
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