User's Manual

page 6/24
Note d’étude / Technical document : URDx– OTL 5635.1– 007 / 70 230 Edition 03
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2. BLOCK DIAGRAM
POWER CONTROL:
POK_IN
POWER SUPPLY:
VBATT (4)
VBACKUP
VGPIO
GND (4)
TRACE:
SPI_CLK
SPI_IRQ
SPI_OUT
SPI_IN
SPI_SEL
UART: TXD
RXD
CTS
RTS
DCD
DSR
DTR
RI
GENERAL IO:
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
ADC:
AUX_ADC0
PWM:
PWM0 (LED1)
PWM1 (LED2)
PWM2 (Buzzer)
SIM:
SIM_CLK
SIM_RST
VSIM
SIM_DATA
AUDIO:
INTMIC_P
HSET_OUT_P
HSET_OUT_N
POWER ON
TRACE PORT
SIM 3V & 1.8V
EXTERNAL
ANALOG INPUT
5 GPIOs
FULL UART PORT
DC
2.8V
Antenna Port:
RF_IN
VBAT
VBAT
VBAT
Figure 1: Block diagram of HiLo module
3. FUNCTIONAL INTEGRATION
The improvement of Silicon technologies heads toward functionality improvement, less power consumption. The
HiLo Module meets all these requirement and use last high end technology. All digital I/Os at the 40 pins
connector are in 2.8V domain which are suitable for most systems except VSIM (the SIM I/Os at 1.8V or 2.9V)
and VBAT which ranges from 3.2V to 4.5V.