User's Manual

HiLo3G-850 User Manual
04 March 2011 - Page 18 / 36
5V signals compatible with a PC.
Figure 19: Connection to a data cable
Pull-up resistors of 100KΩ to VGPIO must be connected to DCD, DSR and RI signals.
Avoid supplying the UART before the HiLo3G-850 is ON, this could result in bad power up sequence. To have a proper
behavior use the signal VGPIO to enable the RS232 Transceiver.
3.5.3 Partial V24 (RX-TX-RTS-CTS)Connection HiLo3G-850 -host
When using only RX/TX/RTS/CTS instead of the complete V24 link, the following schematic could be used.
Figure 20: Partial V24 connection (4 wires) between HiLo3G-850 and host
As DSR is active (low electrical level) once HiLo3G-850 is switched on, DTR is also active (low electrical level),
therefore AT command AT+Ksleep can switch between the two sleeps mode available for HiLo3G-850.
DTR input signal is internally pull upped to VGPIO with a 100KΩ, this result in 28μA of extra consumption.
DCD and RI can stay not connected and floating when not used. Otherwise use 100KΩ pull up to VGPIO.
This configuration allows using the flow control RTS & CTS to avoid any overflow error during the data transfer, CTS is
moreover used to signal when HiLo3G-850 is ready to receive an AT command after a power up sequence or a wake up
from sleep mode.