User's Manual

HiLo3G-850 User Manual
04 March 2011 - Page 16 / 36
3.4 Power Requirements
The host system must supply 3.2V ~ 4.4V to VBAT.
Within normal 2G and 3G operational modes, the maximum average current is about 1.1A depending on RF output
power. In 2G mode peak current can be as high as 2A under matched antenna condition. Peak currents could occur up to
1.75A in the case of a mismatched antenna. In the 3G mode and under antenna mismatch condition, peak current may
increase up to 700mA.
VBAT traces are required to be as short and as wide as possible. Connectors that introduce additional resistance must be
avoided whenever possible. In case it is necessary to change the PCB layer carrying the VBAT lines have several routing
options in parallel available to connect VBAT traces on different layers relative to each other.
VBAT ceramic decoupling capacitors of at least 100μF/10V are required to ensure good RF performance. Placing them
close to the connection pad of the module and connecting them with low resistance tracks to VBAT and GND is strongly
recommended.
Host power must be capable of sourcing enough current to accommodate the maximum power in cases of 2G
transmission bursts. This can be done, for example, by adding a large capacitor with a low ESR value.
PCB tracks must be well dimensioned to support 2.2A maximum current. Voltage ripple caused by serial resistance of
power supply path could result in voltage drop cases.
The HiLo3G-850 does not manage battery charging.
3.5 UART
The HiLo3G-850 has one UART port that can be used in the low-speed, full-speed, and high-speed modes. The UART
communicates with serial data ports that conform to the RS-232 interface protocol. With a properly written and user-
defined download program, the UART can be used as the serial data port for testing and debugging.
Management of external access to the V24 interface, in order to allow easy software upgrades is recommended.
Baud rate up to 4Mbps
Unused signals remain disconnected.
Signal name
Signal use (DTE point of view)
UART_DSR
Signal UART interface is ON
UART_DCD
Signal data connections in progress
UART_TX
Transmit data
UART_CTS
Signal HiLo3G-850 is ready to receive AT commands, has woken
up
UART_RX
Receive data
UART_RTS
Wakes up the module when Ksleep=1 is used
UART_RI
Signal incoming calls (voice and data), SMS, etc.
UART_DTR
Prevents the HiLo3G-850 from entering into the sleep mode
Switches between the data mode and the command modes
Wakes up the module.
3.5.1 Complete V24—Connection HiLo3G-850 -host
A V24 interface is provided on the 40 pins of the HiLo3G-850 module with the following signals: RTS/CTS, RXD/TXD,
DSR, DTR, DCD, RI.
The use of this complete V24 connection is required whenever your application exchanges data.