User's Manual

Note d‘étude / Technical document :
URD1– OTL 5696.1– 003 / 72361 Edition 02
HILO 3G Application Note
17 January 2011 - Page 5 / 38
Figures List
Figure 1: HiLo3G module Block diagram ................................................................................................................ 7
Figure 2: HiLo3G module connector side ................................................................................................................ 8
Figure 3: HiLo3G module back side ......................................................................................................................... 8
Figure 4: SIM Card signals ....................................................................................................................................... 9
Figure 5: EMC and ESD protection components close to SIM ................................................................................ 9
Figure 6: Serial resistors for protection of long SIM bus lines ............................................................................... 10
Figure 7: Primary PCM mode timing parameter .................................................................................................... 11
Figure 8: Auxiliary PCM mode timing parameter .................................................................................................. 12
Figure 9: Analog audio connections ....................................................................................................................... 13
Figure 10: Filter and ESD protection for microphone ............................................................................................ 13
Figure 11: Filter and ESD protection for 32 ohms speaker .................................................................................... 14
Figure 12: Example of D class TPA2010D1 1Watt audio amplifier connections .................................................. 14
Figure 13: Microphone performance requirements ................................................................................................ 15
Figure 14: Speaker performance requirements ....................................................................................................... 16
Figure 15: Buzzer connection ................................................................................................................................. 16
Figure 16: Network LED connection ...................................................................................................................... 17
Figure 17: Complete V24 connection between the HiLo3G and the host............................................................... 18
Figure 18: C ........................................................ 19
Figure 19: Connection to a data cable..................................................................................................................... 19
Figure 20: Partial V24 connection (4 wires) between HiLo3G and host ................................................................ 20
Figure 21: Partial V24 connection (2 wires) between HiLo3G and host ................................................................ 21
Figure 22: Programmable GPIO configurations ..................................................................................................... 22
Figure 23: Backup battery or 10μF capacitor internally charged ............................................................................ 23
Figure 24: Power on sequence ................................................................................................................................ 25
Figure 25: Power off sequence ............................................................................................................................... 25
Figure 26: Diagram for the power on ..................................................................................................................... 26
Figure 27: Diagram for the sleep mode .................................................................................................................. 27
Figure 28: Power off sequence for PWON, VGPIO and CTS ................................................................................ 28
Figure 29: Antenna connection reference ............................................................................................................... 30
Figure 30: Spring contact reference ........................................................................................................................ 30
Figure 31: Ground HiLo3G to customer board ....................................................................................................... 31
Figure 32: Layout of audio differential signals on a layer n ................................................................................... 34
Figure 33: Adjacent layers of audio differential signals ......................................................................................... 34
Figure 34: Reference 6 layers PCB stack ............................................................................................................... 35