User's Manual

Note d‘étude / Technical document :
URD1– OTL 5696.1– 003 / 72361 Edition 02
HILO 3G Application Note
17 January 2011 - Page 20 / 38
Pull-up resistors of 100KΩ to VGPIO must be connected to DCD, DSR and RI signals.
Avoid supplying the UART before the HiLo3G is ON, this could result in bad power up sequence. To have a proper
behavior use the signal VGPIO to enable the RS232 Transceiver.
3.5.3 Partial V24 (RX-TX-RTS-CTS)—Connection HiLo3G -host
When using only RX/TX/RTS/CTS instead of the complete V24 link, the following schematic could be used.
Figure 20: Partial V24 connection (4 wires) between HiLo3G and host
As DSR is active (low electrical level) once HiLo3G is switched on, DTR is also active (low electrical level), therefore
AT command AT+Ksleep can switch between the two sleeps mode available for HiLo3G.
DTR input signal is internally pull upped to VGPIO with a 100KΩ, this result in 28μA of extra consumption.
DCD and RI can stay not connected and floating when not used. Otherwise use 100KΩ pull up to VGPIO.
This configuration allows using the flow control RTS & CTS to avoid any overflow error during the data transfer, CTS is
moreover used to signal when HiLo3G is ready to receive an AT command after a power up sequence or a wake up from
sleep mode.
However this configuration does not allow the signaling signals like:
• RI signal used when programmed to indicate an incoming voice or data call or SMS incoming etc…
• DCD signal used to signal the DATA connections
• DSR signal used to signal the module UART interface is ON (need to pull high DSR with 470K ohm to external 3V,
shown as below)