Direction des Recherches et des Développements RUEIL-MALMAISON R&D Center Etablissement de RUEIL-MALMAISON NOTE D'ETUDE / TECHNICAL DOCUMENT REFERENCE ETUDE / PROJECT URD1 – OTL 5696.
NOTE D'ETUDE / TECHNICAL DOCUMENT FICHE RECAPITULATIVE / SUMMARY SHEET Ed Date Référence Rédacteur(s) Relecteur(s) Date Reference Author(s) Reviser(s) 1 15/12/2010 2 17/01/2011 URD1– OTL 5696.1– CC Hsieh 003 / 72361 URD1– OTL 5696.1– CC Hsieh 003 / 72361 AMMARI M. Pages modifiées / Changed pages All AMMARI M. All Observations Comments Document creation Document number changed. 3 4 5 6 7 Note d‘étude / Technical document : URD1– OTL 5696.
SOMMAIRE / CONTENTS 1. OVERVIEW ................................................................................................................................................................... 6 1.1. Document Objectives.............................................................................................................................................. 6 1.2. Reference Documents .......................................................................................................................
6.3 Layout ................................................................................................................................................................... 32 6.4 Mechanical Surrounding ....................................................................................................................................... 32 6.5 Other Recommendation—test for production/design ........................................................................................... 32 7.
Figures List Figure 1: HiLo3G module Block diagram ................................................................................................................ 7 Figure 2: HiLo3G module connector side ................................................................................................................ 8 Figure 3: HiLo3G module back side ......................................................................................................................... 8 Figure 4: SIM Card signals ......
1. OVERVIEW 1.1.Document Objectives The aim of this document is to describe some examples of hardware solutions for developing some products around the SagemCom HiLo3G Module. Most parts of these solutions are not mandatory. Use them as suggestions of what should be done to have a working product and what should be avoided thanks to our experience.
2. Block Diagram HiLo 3G Antenna Antenna Port Power on Signal DC 2.85V Power Control Battery 3.7V 47uF UART Reset USB Master Power Supply USB Slave Full UART GPIO Three GPIO PWM External Analog input ADC Vibrating device Audio Microphone Speaker USB Slave SIM 3V & 1.8V PCM Figure 1: HiLo3G module Block diagram Note d‘étude / Technical document : URD1– OTL 5696.
3. Functional Integration Advancements in Silicon technologies head toward functionality improvement with less power consumption. The HiLo3G module with its industrial 40 pins connector meets all these requirements, using the latest high end technology in a very compact design of only 27 x 27 x 4.8 mm and weighs less than 7 grams. All digital I/Os among the 40 pins are in the 2.9V domain suitable for most systems except SIM I/O's, which can also be in the 1.
3.1.How to connect a SIM card PIN No. C1 C2 C3 C4 C5 C6 C7 C8 Name VCC RST CLK NA GND VPP I/O N/A Figure 4: SIM Card signals The HiLo3G module provides SIM signals to the 40 pins. A SIM card holder with 6 pins must be adopted to use the SIM function. Decoupling capacitors must be added on VSIM,SIM_DATA,SIM_RST,and SIM_CLK signals as close as possible to the SIM card connector to avoid EMC issues and pass SIM card approval tests.
In cases of long SIM bus lines over 100mm, using serial resistors to avoid electrical overshoots on SIM bus signals is recommended. Use 56 Ω for the clock line and 10Ω for the reset and data lines. NC R601 56 SIM_CLK_CARD 8 3 7 SIM_DATA_CARD 2 6 VSIM_CARD 1 5 33pF SIM_GPIO 2.
Figure 7: Primary PCM mode timing parameter Note d‘étude / Technical document : URD1– OTL 5696.
Figure 8: Auxiliary PCM mode timing parameter Note d‘étude / Technical document : URD1– OTL 5696.
3.2.2 Analog Audio Analog audio is connected via MIC_N and MIC_P as input and HSET_N and HSET_P as output to the HiLo3G. Please note that external circuitries are mainly needed for the microphone and speaker. Speaker HiLo3G ESD protection Mic. Figure 9: Analog audio connections 3.2.2.1 Microphone Note Careful attention must be given to the microphone device design because it must not be sensitive to RF disturbances.
To use an external audio amplifier connected to a loud-speaker, use serial capacitors of 10nF on the HiLo3G audio outputs to connect the audio amplifier. Reference Bead: Murata BLM18HD102SN1D Figure 11: Filter and ESD protection for 32 ohms speaker C71 10uC16TAM10 U22 TPA2010D1Y ZFT R112 150kR2F R113 NC C77 A1 C1 C2 IN+ IN- SPK1 BLM18HD102SN1D V_O+ V_O- C80 NC C3 A3 B3 SHUTDOWN* VIN_3.7 100KR2F BLM18HD102SN1D C81 NC A2 B3 R114 B2 1 B1 C73 150kR2F PV_DD 10uC16TAM10 0.
– Supply current Active state Idle state Parameter Full-scale input voltage Gain error (absolute) Output referred noise Input impedance Parameter THD+N ratio Input capacitance Input offset voltage Signal-to-noise ratio 50 10 Test conditions Voltage across either MIC1P and MIC1N, MIC2P and MIC2N, or LINEIN_LP and LINEIN_LN, 0 dB gain Voltage across either MIC1P and MIC1N, MIC2P and MIC2N, or LINEIN_LP and LINEIN_LN, 24 dB gain 0 and 24 dB gain settings for all inputs.
3.2.2.4 Recommended Speaker Characteristics Item to be inspected Input power: rated / max Audio chain impedance Frequency Range Sensitivity (S.P.L) Distortion Acceptance criterion 0.1W (Rate) 32 ohm +/- 10% at 1V 1KHz 300 Hz ~ 4.0 KHz >105 dB at 1KHz with IEC318 coupler 5% max at 1K Hz, nominal input power Figure 14: Speaker performance requirements 3.3 PWM One PWM pin is available on the HiLo3G. It‘s a general purpose PWM which can be used for driving a vibrating device, keypad backlight or LED.
Figure 16: Network LED connection 3.4 Power Requirements The host system must supply 3.2V ~ 4.4V to VBAT. Within normal 2G and 3G operational modes, the maximum average current is about 1.1A depending on RF output power. In 2G mode peak current can be as high as 2A under matched antenna condition. Peak currents could occur up to 1.75A in the case of a mismatched antenna. In the 3G mode and under antenna mismatch condition, peak current may increase up to 700mA.
UART_RX Receive data UART_RTS Wakes up the module when Ksleep=1 is used UART_RI Signal incoming calls (voice and data), SMS, etc. UART_DTR Prevents the HiLo3G from entering into the sleep mode Switches between the data mode and the command modes Wakes up the module. 3.5.1 Complete V24—Connection HiLo3G -host A V24 interface is provided on the 40 pins of the HiLo3G module with the following signals: RTS/CTS, RXD/TXD, DSR, DTR, DCD, RI.
PWRON CTS Figure 18: C In addition, this signal configuration enabled all signals : • RI signal used when programmed to indicate an incoming voice or data call or SMS incoming message, etc. • DCD signal used to signal the GPRS connections • DSR signal used to signal that the module UART interface is ON • DTR signal used to prevent the HiLo3G from entering into the sleep mode, switching between Data and AT commands, hanging up a call or waking up the module etc.
Pull-up resistors of 100KΩ to VGPIO must be connected to DCD, DSR and RI signals. Avoid supplying the UART before the HiLo3G is ON, this could result in bad power up sequence. To have a proper behavior use the signal VGPIO to enable the RS232 Transceiver. 3.5.3 Partial V24 (RX-TX-RTS-CTS)—Connection HiLo3G -host When using only RX/TX/RTS/CTS instead of the complete V24 link, the following schematic could be used.
470K Vcc_3V • DTR signal used to prevent HiLo3G from entering into sleep mode or to switch between Data and AT commands or to hang up a call or to wake up the module etc… 3.5.4 Partial V24 (RX-TX)—Connection HiLo3G -host When using only RX/TX instead of the complete V24 link, the following schematic could be used.
AT command AT+Ksleep can switch between the two sleep modes available for HiLo3G. DTR input signal is internally pulled up to VGPIO with a 100KΩ, this result in 28μA of extra consumption As CTS is active (low electrical level) once HiLo3G is switched on, RTS is also active (low electrical level), therefore AT command AT+Ksleep can switch between the two sleep modes that are available for HiLo3G. The HiLo3G's firmware allows the rise of CTS during the sleep state even when looped to RTS signal.
3.8 Backup Battery 3.8.1 Backup Battery Function Feature 3.8.1.1 With Backup Battery A backup battery can be connected to the module in order to supply internal RTC (Real Time Clock) when the main power supply is removed. Thus, when the main power supply is removed, the RTC is still supplied with power and the module keeps the time register running. • If VBAT < 3V, internal RTC is supplied by VBACKUP. • If VBAT ≧3V, internal RTC is supplied by VBAT. 3.8.1.
3.9 USB There is one set USB_DP and USB_DN bi-directional differential USB data lines are compliant to the USB2.0 specification. HiLo3G is USB-Slave while customer application is USB-Master. • Integrated high-speed USB PHY • USB 2.0 specification-compliant as a peripheral •The USB 2.0 specification requires hosts such as PCs to support all three USB speeds, namely low-speed (1.5 Mbps), fullspeed (12 Mbps) and high-speed (480 Mbps). The USB 2.
After a few seconds, the CTS goes to the active state when the module is ready to receive AT commands. VGPIO is a supply output from the module that can be used to check if the module is alive. • When VGPIO = 0V the module is OFF • When VGPIO = 2.9V the module is ON Figure 24: Power on sequence Figure 25: Power off sequence Send AT COMMAND ―AT+CPOF ― to power off module. 4.2.1.
VBACKUP raise to 3V PWON raise to 1.8V 4.3 Power on and Sleep Diagrams Those 2 diagrams show the behaviors of the module and the DTE during the power on and then in the sleep modes. Note: The module cannot enter sleep mode if USB bus is connected. Figure 26: Diagram for the power on Note d‘étude / Technical document : URD1– OTL 5696.
Figure 27: Diagram for the sleep mode Note d‘étude / Technical document : URD1– OTL 5696.
4.4 Module Power off 4.4.1 UART Interface To stop the module, use the AT command AT+CPOF. If the PWON is not pulled down the module will switch to OFF mode after the AT command, otherwise the module restarts immediately (an OFF sequence is performed followed by a power ON sequence). Figure 28: Power off sequence for PWON, VGPIO and CTS 4.4.
5. ESD & EMC Recommendation Using human body model from JEDEC JESD 22-A114 standard, HiLo3G can hold 2KV on each of the 40 pins and contact areas such as antenna pads and connector. 5.1 Handling HiLo3G HiLo3G are packaged in boxes. HiLo3G contains electronic circuits sensitive to human hand's electrostatic electricity. Handling without ESD protection could result in permanent damages or even destruction of the module. 5.
6. Radio Integration HiLo3G incorporates the technology for RF transceiver that converts received signals directly from RF-to-baseband and transmits signals directly from baseband-to-RF (known as direct conversion or zero intermediate frequency (ZIF) processing). This technique eliminates the need for large IF surface acoustic wave (SAW) filters and supporting IF and LO circuits. 6.
6.1.3 Antenna Notice Antenna for HiLo3G should be resonated in the operating bands (GSM 850, 900, 1800, 1900 + UMTS band 1, 2, 5,8) depending on HiLo3G reference. Pay attention to the RF-impedance of the HiLo3G (50Ω) Use low loss antenna cable (max. 0.5dB). To avoid interference choose an antenna type radiating off the device. Circular polarized antennas are preferred. Verify the operation of the antenna by measurement of the total radiated power.
6.3 Layout Isolate RF line and antenna from other bus or signals No signals on 50 ohms area and if that is not possible, add ground shielding using different layers. Do not add any ground layer under the antenna contact area. Do not add signal unvarnished layout trace on the first layer of the customer board, or unvarnished via holes under the module shield area or it will result on short circuit on those signals. This is mandatory.
7.2 Electronics and layout Avoid Distortion & Burst noise Audio signals must be symmetric (same components on each path). Differential signals must be routed parallel. Audio layer must be surrounded by 2 ground layers. The link from one component to the ground must be as short as possible. If possible separate the PCB of the microphone and the one of the speaker. Reduce as many as possible the number of electronics components (loss of quality, more dispersion). Audio tracks must be larger than 0.
8.1.2 Power supplies Layer for power supply signals (VBAT, VGPIO) is recommended. Any loop of power signals layout must be avoided on the design. Suitable power supply (VBAT, VGPIO) track width and thickness. 8.1.3 Clocks Clock signals must be shielded between two grounds layer and bordered with ground vias. 8.1.
8.1.7 Shielding A few shielding comments are provided for designer consideration: At least the following devices and circuits should be shielded: • High-speed memory • RF front-end components • Crystal circuits • DC/DC circuits • RF circuitry Recommended shield partitioning: • RF matching components, do not locate matching inductors too close to shield walls (this may cause electromagnetic coupling and inductor de-Q). • Memory devices must be shielded.
9. Label The HiLo3G is labeled with its own FCC ID (VW3HILO3G) on its shield side. When the module is installed in customer‘s product, the FCC ID label on the module will not be visible. To avoid this case, an exterior label must be stuck on the surface of customer‘s product signally to indicate the FCC ID of the enclosed module. This label can use wording such as the following: ―Contains Transmitter module FCC ID: VW3HILO3G‖ or ―Contains FCC ID: VW3HILO3G‖. 10. CE/FCC/IC warning statement 10.
10.3 IC Regulations: Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. IMPORTANT NOTE: IC Radiation Exposure Statement: This equipment complies with IC RSS-102 radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20cm between the radiator & your body.
10.5 Declaration of Conformity We, Sagemcom SAS, Address: 250 Route de l'Empereur, 92848 Rueil Malmaison Cedex France Declare under our own responsibility that the product: Model: HiLo3G Intended use: Quad-Band GSM/GPRS/EDGE and Tri-Band WCDMA/HSDPA MODULE Complies with the essential requirements of Article 3 of the R&TTE 1999/5/EC Directive, if used for its intended use and that the following standards have been applied: Health (Article 3.
