User's Manual

Sipeed Technology
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Sipeed M1w User Manual v1.0
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V1.0 Edited on April 23, 2019 ; Original document
FEATURES OVERVIEW
CPU : RISC-V Dual Core 64bit, 400Mh adjustable
Powerful dual-core 64-bit open architecture-based
processor with rich community resources
FPU Specifications IEEE754-2008 compliant high-performance pipelined FPU
Debugging Support High-speed UART and JTAG interface for debugging
Neural Network Processor (KPU)
Supports the fixed-point model that the mainstream
training framework trains according to specific restriction
rules
There is no direct limit on the number of network layers,
and each layer of convolutional neural network
parameters can be configured separately, includ- ing the
number of input and output channels, and the input and
output line width and column height
Support for 1x1 and 3x3 convolution kernels
Support for any form of activation function
The maximum supported neural network parameter size
for real-time work is 5MiB to 5.9MiB
The maximum supported network parameter size when
working in non-real time is (flash size - software size)
Audio Processor (APU)
Up to 8 channels of audio input data, ie 4 stereo
channels
Simultaneous scanning pre-processing and
beamforming for sound sources in up to 16 directions
Supports one active voice stream output
16-bit wide internal audio signal processing
Support for 12-bit, 16-bit, 24-bit, and 32-bit input data
widths Multi-channel direct raw signal output
Up to 192kHz sample rate
Built-in FFT unit supports 512-point FFT of audio data
•Uses system DMAC to store output data in system
memory
Static Random-Access Memory (SRAM)
The SRAM is split into two parts, 6MiB of on-chip
general-purpose SRAM memory and 2MiB of on-chip AI
SRAM memory, for a total of 8MiB
Field Programmable IO Array (FPIOA/IOMUX)
FPIOA allows users to map 255 internal functions to 48
free IOs on the chip
Digital Video Port (DVP) Maximum frame size 640x480
FFT Accelerator
The FFT accelerator is a hardware implementation of the
Fast Fourier Transform (FFT)