FPGA35S6045HR FPGA35S6100HR FPGA Module User’s Manual BDM-610010045 Rev. C RTD Embedded Technologies, Inc.
RTD Embedded Technologies, Inc. 103 Innovation Boulevard State College, PA 16803 USA Telephone: 814-234-8087 Fax: 814-234-5218 www.rtd.com sales@rtd.com techsupport@rtd.
Revision History Rev A Rev B Rev C Initial Release Corrected pin names in Table 5 on page 13. Corrected FPGA Bank designations in CN4 & CN9: Digital I/O Connector on page 14. Added IDAN connector section. Change IDAN JTAG signals from P2 to P3 in Table 11 on page 18.
Table of Contents 1 2 3 4 5 6 Introduction 7 1.1 Product Overview........................................................................................................................................................................ 7 1.2 Board Features ........................................................................................................................................................................... 7 1.3 Ordering Information .............................................
6.1 BAR0 – FPGA Example Register Map ..................................................................................................................................... 25 6.1.1 R_ID (Read) 25 6.1.2 R_STATUS (Read) 25 6.1.3 R_EEPROM (Read/Write) 25 6.1.4 R_PORT0_IN (Read) 26 6.1.5 R_PORT0_OUT (Write) 26 6.1.6 R_PORT0_DIR (Write) 26 6.1.7 R_PORT1_IN (Read) 26 6.1.8 R_PORT1_OUT (Write) 26 6.1.9 R_PORT1_DIR (Read/Write) 26 6.1.10 R_PORT2L_IN (Read) 26 6.1.11 R_PORT2L_OUT (Write) 26 6.1.
Table of Figures Figure 1: Board Dimensions ................................................................................................................................................................................... 10 Figure 2: Board Connections .................................................................................................................................................................................. 11 Figure 3: Bottom Solder Jumper Locations ..................................
1 Introduction 1.1 Product Overview The FPGA35S6 series of FPGA boards are designed to provide platform to create any digital I/O that is required for your application. It interfaces with the PCIe bus and features a Xilinx Spartan 6 FPGA with a 27 MHz oscillator and 1Gb of DDR2 SDRAM. There 48 5V tolerant I/O and 40 3.3V tolerant high speed I/O. 1.
1.
2 Specifications 2.1 Operating Conditions Table 2: Operating Conditions Symbol Vcc5 Vcc3 Vcc12 Ta Ts RH Parameter 5V Supply Voltage 3.3V Supply Voltage 12V Supply Voltage Operating Temperature Storage Temperature Relative Humidity MTBF Mean Time Before Failure Test Condition Min 4.75 n/a n/a -40 -40 0 Non-Condensing Telcordia Issue 2 30°C, Ground benign, controlled Max 5.25 n/a n/a +85 +85 90% TBD Unit V V V C C % Hours 2.
3 Board Connection 3.1 Board Handling Precautions To prevent damage due to Electrostatic Discharge (ESD), keep your board in its antistatic bag until you are ready to install it into your system. When removing it from the bag, hold the board at the edges, and do not touch the components or connectors. Handle the board in an antistatic environment, and use a grounded workbench for testing and handling of your hardware. 3.2 Physical Characteristics Weight: Approximately 63.5 g (0.14 lbs.
3.3 Connectors and Jumpers CN8: High Speed Digital I/O CN9: Digital I/O CN4: Digital I/O JP4, JP5 & JP6: Pull up/Pull down Jumper JP1, JP2 & JP3: Pull up/Pull down Jumper CN3: Programming Header CN1 & CN2: PCIe Connector Figure 2: Board Connections RTD Embedded Technologies, Inc. | www.rtd.
B2 B1 1 1 Figure 3: Bottom Solder Jumper Locations 3.3.1 EXTERNAL I/O CONNECTORS CN3: Xilinx JTAG Programming Header Connector CN3 provides a connection to the Xilinx JTAG programming header. The pin assignment for CN3 is shown below. This connector header mates with the Xilinx OEM programming cable. Table 4: CN3 Programming Header 3.3V VRef TMS TCK TDO TDI N/C N/C RTD Embedded Technologies, Inc. | www.rtd.
CN8: High Speed Digital I/O Connector Connector CN8 provides 40 digital I/O lines, along with a +5V pin and ground pins. These signals are 3.3V tolerant. The signal names reflect the signal names I n the Xilinx UCF file with the device pin out. CN8 is attached to Bank 1, and supports any of the Spartan 6 I/O Standards that use a 3.3V VCCO and no reference voltage. This includes LVTTL, LVCMOS33 input and output, and LVDS_33 input. LVDS output is not supported in Bank 1.
CN4 & CN9: Digital I/O Connector Connectors CN4 and CN9 each provide 24 digital I/O lines, along with a +5V pin and ground pins. All I/O have pull up/pull down resistors that are controlled by jumper options, also shown in the table. These signals are 5V tolerant. The signal names reflect the signal names I n the Xilinx UCF file with the device pin out. CN4 and CN9 are attached to Bank 2 and 0 respectively, and support any of the Spartan 6 I/O Standards that use a 3.3V VCCO and no reference voltage.
JP7: Reserved JP7 is reserved, and must be left open. 3.3.1 SOLDER JUMPER B1: Pull up Voltage Solder jumper B1 are used to set the pull up voltage for JP1, JP2 and JP3. Table 9: B1 Pull up Voltage Setting 1-2 2-3 Description Sets Pull up voltage to 3.3V Sets Pull up voltage to 5V B2: Pull up Voltage Solder jumper B1 are used to set the pull up voltage for JP4, JP5 and JP6. Table 10: B2 Pull up Voltage Setting 1-2 2-3 RTD Embedded Technologies, Inc. | www.rtd.com Description Sets Pull up voltage to 3.
3.4 Steps for Installing 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. Always work at an ESD protected workstation, and wear a grounded wrist-strap. Turn off power to the PC/104 system or stack. Select and install stand-offs to properly position the module on the stack. Remove the module from its anti-static bag. Check that pins of the bus connector are properly positioned. Check the stacking order; make sure all of the busses used by the peripheral cards are connected to the cpuModule.
4 IDAN Connections 4.1 Module Handling Precautions To prevent damage due to Electrostatic Discharge (ESD), keep your module in its antistatic bag until you are ready to install it into your system. When removing it from the bag, hold the module by the aluminum enclosure, and do not touch the components or connectors. Handle the module in an antistatic environment, and use a grounded workbench for testing and handling of your hardware. 4.2 Physical Characteristics Weight: Approximately 0.42 Kg (0.
4.3 Connectors and Jumpers P2 & P3: Digital I/O Connector Connector Part #: VALCONN HDB-62S Mating Connector: VALCONN HDB-62P Connectors P2 and P3 each provide 24 digital I/O lines, along with a +5V pin and ground pins. All I/O have pull up/pull down resistors that are controlled by jumper options, also shown in the table. These signals are 5V tolerant. The signal names reflect the signal names I n the Xilinx UCF file with the device pin out.
Table 11: P2 and P3 Pin Assignments Row 1 IDAN P2 Pin Row 2 Row 3 36 57 16 37 58 17 38 59 18 39 60 19 40 61 20 41 62 21 42 Signal GND port0_p[11] GND port0_n[11] GND +5V GND Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pull Jmpr CN4 Pin 44 45 46 47 48 49 50 Row 1 IDAN P3 Pin Row 2 Row 3 36 57 16 37 58 17 38 59 18 39 60 19 40 61 20 41 62 21 42 Signal GND port1_p[11] GND port1_n[11] GND +5V GND Reserved jtag_vref GND jtag_tms GND_TCK jtag
Table 12: P4 Pin Assignments Row 1 9 IDAN P4 Pin Row 2 Row 3 30 51 10 31 52 11 32 53 12 33 54 13 34 55 14 35 56 15 36 57 16 37 58 17 38 59 18 39 60 19 40 61 20 41 62 21 42 RTD Embedded Technologies, Inc. | www.rtd.
4.3.1 BUS CONNECTORS CN1 (Top) & CN2 (Bottom): PCIe Connector The PCIe connector is the connection to the system CPU. The position and pin assignments are compliant with the PCI/104-Express Specification. (See PC/104 Specifications on page 29) The FPGA35S6 is a “Universal” board, and can connect to either a Type 1 or Type 2 PCIe/104 connector. 4.3.
4.4 Steps for Installing 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. Always work at an ESD protected workstation, and wear a grounded wrist-strap. Turn off power to the IDAN system. Remove the module from its anti-static bag. Check that pins of the bus connector are properly positioned. Check the stacking order; make sure all of the busses used by the peripheral cards are connected to the cpuModule.
5 Functional Description 5.1 Block Diagram The Figure below shows the functional block diagram of the FPGA35S6. The various parts of the block diagram are discussed in the following sections. X2 Level Shifter PCIe x1 Link Xilinx Spartan 6 EEPROM High Speed Digital I/O CN8 PCIe Bus DDR2 SRAM Digital I/O CN4 and CN9 X2 Oscillator Figure 7: FPGA35S6 Block Diagram 5.2 Oscillator The FPGA35S6 features a 27 MHz oscillator for clock based operations in the FPGA. 5.
5.5 Digital I/O The FPGA35S6 digital I/O on connectors CN4 and CN9 use the circuitry shown below to level shift the input voltage from 5V to 3.3V allowing the I/O on these connectors to be 5V tolerant. CN4/CN9 33Ω Digital I/O Xilinx Spartan 6 Level Shifter 10KΩ +5V/3.3V Figure 8: CN4/CN9 Digital I/O Circuitry RTD Embedded Technologies, Inc. | www.rtd.
6 Register Address Space This is the register address space for the example FPGA that is given with the FPGA35S6. 6.1 BAR0 – FPGA Example Register Map Table 16: FPGA Example Register Map Offset 0x00 0x04 0x08 0x10 0x14 0x18 0x20 0x24 0x28 0x30 0x34 0x38 0x40 0x44 0x48 0x50 0x54 0x58 0x5C 0x60 0x64 6.1.
6.1.4 R_PORT0_IN (READ) This is the input register for the port0. This reads the current value the I/O. 6.1.5 R_PORT0_OUT (WRITE) This is the output register for the port0. The value to be output, direction must be set to output. 6.1.6 R_PORT0_DIR (WRITE) This is the direction register for port0. Indicates the direction of each pin ‘0’ = input ‘1’ = output 6.1.7 R_PORT1_IN (READ) This is the input register for the port1. This reads the current value the I/O. 6.1.
6.1.19 R_DDR_STATUS (READ) This is a status register for the DDR2 memory interface. B0: Read error B1: Read overflow B2: Read empty B3: Read full B4: Write error B5: Write underrun B6: Write empty B7: Write full B[14:8]: Read count B[22:16]: Write count B[24]: Command full B[25]: Command empty B[31]: Calibration done RTD Embedded Technologies, Inc. | www.rtd.
7 Troubleshooting If you are having problems with your system, please try the following initial steps: Simplify the System – Remove modules one at a time from your system to see if there is a specific module that is causing a problem. Perform you troubleshooting with the least number of modules in the system possible. Swap Components – Try replacing parts in the system one at a time with similar parts to determine if a part is faulty or if a type of part is configured incorrectly.
8 Additional Information 8.1 PC/104 Specifications A copy of the latest PC/104 specifications can be found on the webpage for the PC/104 Embedded Consortium: www.pc104.org 8.2 PCI and PCI Express Specification A copy of the latest PCI and PCI Express specifications can be found on the webpage for the PCI Special Interest Group: www.pcisig.com RTD Embedded Technologies, Inc. | www.rtd.
9 Limited Warranty RTD Embedded Technologies, Inc. warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from RTD Embedded Technologies, Inc. This warranty is limited to the original purchaser of product and is not transferable.
RTD Embedded Technologies, Inc. 103 Innovation Boulevard State College, PA 16803 USA Telephone: 814-234-8087 Fax: 814-234-5218 www.rtd.com sales@rtd.com techsupport@rtd.com Copyright 2014 by RTD Embedded Technologies, Inc. All rights reserved.
