User`s manual

42
The following table lists signals of the AT portion of the PC/104 bus.
Notes:
Keying pin positions are blanked to prevent misalignment of stacked modules. This is a feature of
the PC/104 specification and should be implemented on all mating PC/104 modules.
Signals marked with (*) are active-low.
0V is ground
All bus lines can drive a maximum current of 6mA at TTL voltage levels.
PC/104 AT Bus Connector, CN2
Pin Row C Row D
10V0V
2 SBHE* MEMCS16*
3 LA23 IOCS16*
4LA22IRQ10
5LA21IRQ11
6 LA20 IRQ12 Used in-
ternally
7LA19IRQ15
8LA18IRQ14
9 LA17 DACK0*
10 MEMR* DRQ0
11 MEMW* DACK5*
12 SD8 DRQ5
13 SD9 DACK6*
14 SD10 DRQ6
15 SD11 DACK7*
16 SD12 DRQ7
17 SD13 +5V*
18 SD14 MASTER*
19 SD15 0V
20 (Keying pin) 0V