FEB.
FEB.
SDE-1000/3000 FEB. 5.
SDE-1000/3000 (SDE-1000) (SDE-1000) (SDE-1000) (SDE-1000) (SDE-1000) (SDE-3000) (SDE-3000) (SDE-3000) FUSE 12559105 12559510 1A CEE T400mA 12559504 CEE T100mA 12559506 CEE T160mA 100/117V 220/240V 220/240V 220/240V (SDE-1000) (SDE-3000) IC 15229811 MB63H101 15179141 MSM80C49-44RS M5K4164NP-20 M54563 SN74LS48N HD14001 BP HD14011 BP HD14049 BP HD14174 BP 15169355 15159101H0 15159104H0 15159112H0 15159133 15189111J1 15189163 15219116 15189136 15189141 15199106F0 15169102H0 15169117H0 151693
FEB. 5,1984 SDE-1000/3000 CAPACITOR 13549884M0 ECQM-6103MZ O.OlyF 1OOV Polypropylene 13589455M0 13589456M0 ECQ-U2A103MF 220/240V 117V Polypropylene ECQ-U1A103MC O.OlyF O.OlyF 13639154M0 ECEA1CS102 13639194M0 ECEA1VS102 13639923M0 ECEA1CN470S YM92PS122-2A O,OO12yF YM92PS152-2A O.OO15yF CS15E1VR22K1S 0.22yFx2 YM92PS102-2A O.OOlyF CS15E1V4R7K1S 4.
SDE-1000/3000 CIRCUIT DESCRIPTIONS General Description SDE-1000/3000, Digital Delay Line, use RAMs as memory device in which audio signals are stored by means of PCM (Pulse Coded Modulation) method. The delay unit first samples the input audio signal to have a series of discrete values of the signal amplitude at point.
FEB. 5,1984 SDE-1000/3000 D/A CONVERTER As the name implies, IC12 Main Controller is the heart of the Delay Line. All the delay circuits will not work correctly should the Main Controller fail to A0-A7 When the time determined by DELAY TIME has passed, some parts of A/D receive adequate clocks from IC23. These pins feed RAMs with addresses: Refresh, Row and Column.
SDE-1000/3000 FEB.
FEB. 5.
SDE-1000/3000 MSCK, HDCK & CLOCK GENERATOR CONTROL SIGNALS IN DIFFE RENT MODES The frequency of Clock Generator is as follows (approx): 2.7MHz at Normal 1.7MHz at TIME X1.5 2.7M-3.3MHZ at MOD max. 1.7M-2MHz at TIME X1.5/M0D max. FEB. 5,1984 CPU The CPU is provided with a battery backup to retain switch, delay time and preset settings. MSCK - Clocks the internal Timing Generator that times the most of digital circuits. HDCK - The frequency of HDCK is MSCK or 43Hz at normal mode.
CORRECTION PAGE 10 MSCK, HDCK & CLOCK GENERATOR The frequency of Clock Generator is as follows (approx): 2.7MHz at Normal 1.7MHz at TIME X1.5 2.7M-3.3MHz at MOD max. 1.7M-2M MSCK — Clocks the internal Timing Generato EXPLODED VIEW MSCK times the most of digital circuits. SDE-1000/3000 ^ "' i i HDCK - The frequency of HDCK is\M^J>br 43Hz at normal mode. Used by the CPU as a time base for calibrating Delay Time display. The CPU fails to read switches and jacks if HDCK period is outside 7m-50ms.
FEB. 6.1984 n SDE-1000/3000 SDE-3000 DESCRIPTION CV LINEARIZER The following sections concentrate to the circuits particular to SDE-3000. The output voltage at IC49A pin 1 is normally 0V. time, the D/A converter outputs the same successive voltages which are For other circuits not described, refer to those in SDE-1000. Has a unique voltage response curve to compensate for nonlinear V/C charac attenuated by IC10 by 1, 10 and 100'respectively before comparison.
SDE-100073000 PEAK HOLD & COMPARATOR (ICs 6 and 7) FEB. 5,1984 When in delay mode (D/A cycle, IC31 DB5=H and DB6=L), companding data is latched into IC32 on rising edge of DB4, selected by IC34 (pin 1=H), gated The positive and negative peaks of a samped signal are peak-held and detected by IC35C and D, then routed to IG10.
DIN of IC31 TP-1 Freed from comDandinq effect n A/D staircase must step by 1/2 in amplitude. If not, or uncertain because of lower bits, check suspective bit(s) onD11-D0of IC31. P.B.HJR.H. READ/ WRITE POINTER RS 64 18k WORD RS 16 16k WORD The waveform (and sound) will be disturbed at the moment when defective bit is reproduced. Check for jitter or glitch (pulse) at TP-1. If doubtful, proceed to I IC36. IC38 Companding RAMS IC41. IC43 3.
SDE-1000/3000 FEB. 5,1984 SDE-1000 ENGINEERING CHANGE Earier SDE-1000's have factory-modifications on INPUT Switch, Head Amp, Expander and Compressor as shown in the table below. The modifications add the following features (one by one) to the unit when it is used with UNIGAIN set in -20dBm. * When need arises to implement one o1 the aboves to a given unit with serial number prior to 374800, the final values in the bottom of list should be ap plied since these improvements closely elate to each other.
FEB. 5,1984 SDE-1000/3000 SDE-1000 ADJUSTMENT 1. LEVEL METER CALIBRATION 1-1. Set UNIGAIN (Rear panel) to -20dBm. 1-2. Connect audio generator (AG) to INPUT jack and 6. EXPANDER TOTAL HARMONIC DISTORTION OFF 1-3. Set RT8 at the point where +3dB LED just com TEST POINT: DELAY OUT (connect to scope - - pletely fades out. set AG for -20dBm, 1kHzf sine. DC coupling) 5-1. Set DELAY TIME to X1 and UNIGAIN to 2. DELAY TIME MVTATT DELAY OUT SRoland 5-2. Feed the same signal as for 4-2. 5-3.
SDE-1000/3000 SWITCH BOARD 7411608005 SDE-1000 MAIN BOARD 7411606031 (pcb 2291058400) (pcb 2291058201) See P.19 for POWEFSUPPLY BOARD View from foil side iw? ^r^PPIpl|J||m^ f 1/"' ^#111 tV kaftM»\ il^V'^a"' ©C5s'.*—- Ml X •xPi»_9*» ; Itt^tt > 0*"0 0 I ® ® ® ® ® ® - S S 2 g s LED BOARD 7411607001 (pcb 2291058300) View from foil side 16 FEB.
ID CD O o o o UJ T a CO t N SSS88 ice clilsssassas BBBBBBBBBBBBBBBBBB 1 X 1 5 1 > MT-74116060 r c T CO T OC O 1—" MAIN BOARD BBBBBSBBfi UNLESS OHCRWISE SPEDFIEO ALL <*0> TflANSiSTORS ON MAIN eOtitOARE 2SAII6 UNLESS OTHERWISE 8FEOFIED ALL NPN TRANSISTORS ON MAM BOARD ARE 2SC26O3 >■ UNLESS OTHERWISE SPEOFCD ALL DIODES ARE ISSI33 1 c ii c \ 1—r~"—r | Control Logic SWITCH BOARD —I—T POWER SUPPLY BOARD VtJ-VtJ t1V«OOmA«IODtF f IN r PT RATING IDC.
til 8 FOOT CONTROL I MODULATION
Q $ CIRCUIT OlAGfiAM f I I DC SUPPLY, TO 4053 IC5i1,12,13,16.
FEB. 5,1984 SDE-1000/3000 a 6 10 9 , 11 , 12 , 13 , Buffer Selector T*t2S:2sceosr 14 , 16 , 16 . 17 . 18 20 19 .
i,i-t. | ti.t.i"'* u'- • -'^j r.;, •;• .'•■-•: ■::- ■ ---• r^.-::--.
SDE1000/3000 i. 6 t 37 , 38 , 39 , 40 . 42 41 ,. 43 , 44 B Switch Board 8W4117-080 C D E F RAM BOARD 7411711002 (pcb 2291083800) View from foil side G H I J « K ♦» IJK8 I*** L M N as O P ui $lslE o tstmiJMki a R 8 PT RATIHOS Rtdlted I3JBVOC«t VtlVt* t MVOC ■ U V h POWER SUPPLY BOARD 7411709000 (pcb22d1058500) Common to SOE tOOO and SOE^OOO f mm. Fuie label*. Capacitor Ci wsto&BA. Specify modal and line voltage when ordering lot complete my.
.» ■l. . DUAL SPOT HI-303 ft HI-307 DUAL OWt HI-30i ft M1-30S |TOP VIEW) NClT J* 01 •1 JL u o$ 11)04 01 pot «1 1*1 v- ANALOG SWITCH BOARD 22*1091900 Temtiorarily used for SN 372900-396099 - Substitute for ICB HI-302 and IC10 MI-303 - _ Analog Swrtteh Board 2291091900 1* aqulwrient to Hl-303 and H14102 In operation and H Stalled on «m* un»U baetu» ^^r^"^^; When the PCB needs replacing, use ty.
rco. o, loo** ■■ 'I SDE-3000 ADJUSTMENT 1. VOLTAGES CHECK IC24 4514 8.'tltv8 Front Panel 2. i;^l"®fdp S INPUT LEVEL METER IEW) OFF 2-1 Set UNIGAIN (Rear panel) to +4dBm. 2-2. Connect audio generator (AG) to INPUT Jack and 23. Set VR2«t the point where +3dBm LED Juttcom pletely fedes out. set AG output for +4dBm, 1kHz, sine. 3. VCO 3-1. Set DELAY TIME (Rear panel) to XI. 3-2. Press and hold DELAY TIME button until TIME display reads maximum value. 4. 3-3. Press TIME X2 (ON). 34.
axA**m SDE-1000/3000 FEB. 5,1984 MAIN BOARD SDE-3000 7411706026 (pcb 2291057901) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 SW2 UNIGAIN(SUF-12) ;E F' C on +4dBm -20dBm i3> t: 'o ' t ;o ;A b OFF ; u SW1 BYPASS(SUE-12) Top View SW1 BYPASS(SUE-12) ° :F e: °: OFF -20dBm o ! b" o :o • d ,o .d c: o, o1 t r6 ;B a! +4dBm 'O ' ON F1.
SDE-1000/3000 EXAMPLES OF RAM FAILURE —No data on one RAM pin of Main Controller- INPUT -18dBm 1kHz FEB. 5,1984 UM1 (IC11) RAM2 (IC10) RAM3 (IC9) RAM1 RAM2 RAM3 SDE-1000 TP-3 5V/div INPUT -18dBm 1kHz RAM1 defective RAM17& RAM1 (IC11) IC16 pin6 2V/div 0.2ms/div IC28 pin6 5V/div TP-3 TP-3 5V/div 5V/div 0.2ms/div TP-1 20V/div 5/is/div SDE-3000 INPUT -10dBm 1kHz TP-1 INPUT -10dBm 1kHz All RAMs intact TR45/TR50 emitter 0.
