Datasheet

Technical Note

14/31

BD5446EFV

www.rohm.com

2011.06 - Rev.C

●Audio Interface format and timing

Recommended timing and operating conditions (MCLK, BCLK, LRCLK, SDATA)

※1 This regulation is to keep rising edge of LRCK and rising edge of BCLK from overlapping.

※2 This regulation is to keep rising edge of SYS_CLK and rising edge of BCLK from overlapping.

Parameter Symbol

Limit

Unit

Min. Max.

1 SYS_CLK frequency fSYS_CLK 8.192 12.288 MHz

2 LRCLK frequency fLRCLK 32 48 kHz

3 BCLK frequency fBCLK 2.048 3.072 MHz

4 Setup time, LRCLK※1 tSU;LR 20 － ns

5 Hold time, LRCLK※1 tHD;LR 20 － ns

6 Setup time, SDATA tSU;SD 20 － ns

7 Hold time, SDATA tHD;SD 20 － ns

8 Setup time, BCLK※2 tSU;BC 2.5 － ns

9 Hold time, BCLK※2 tHD;BC 3.5 － ns

SYS_CLK

1/ｆ

LRCLK

1/fLRCLK

BCLK

1/fBCLK

LRCLK

BCLK

SDATA

tHD;LR tSU;LR

tHD

;

/SYS_CLK

;

tSU

;

SYS_CLK

BCLK

tHD

;

tSU

;

Fig-27 Audio Interface timing (1)

Fig-26 Clock timing

Fig-28 Audio Interface timing (2)