Datasheet
Technical Note
7/18
BR25S□□□ Series
www.rohm.com
2010.12 - Rev.B
© 2010 ROHM Co., Ltd. All rights reserved.
●Features
○Status registers
This IC has status register. The status register expresses the following parameters of 8 bits.
BP0 and BP1 can be set by write status register command. These 2 bits are memorized into the EEPROM, therefore are
valid even when power source is turned off.
Rewrite characteristics and data hold time are same as characteristics of the EEPROM.
WEN can be set by write enable command and write disable command. WEN becomes write disable status when power
source is turned off. R/B is for write confirmation, therefore cannot be set externally.
The value of status register can be read by read status register command.
1. Contexture of status register
Product number bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
BR25S320-W
WPEN 0 0 0 BP1 BP0 WEN R
―
/B
BR25S640-W
BR25S128-W
BR25S256-W
bit
Memory
location
Function
WPEN EEPROM
WPB pin enable / disable designation bit
WPEN=0=invalid
WPEN=1=valid
BP1
BP0
EEPROM EEPROM write disable block designation bit
WEN registers
Write and write status register write enable / disable status confirmation bit
WEN=0=prohibited
WEN=1=permitted
R
―
/B
registers
Write cycle status (READY / BUSY) status confirmation bit
R
―
/B=0=READY
R
―
/B=1=BUSY
2. Write disable block setting
BP1 BP0
Write disable block
BR25S320-W BR25S640-W BR25S128-W BR25S256-W
0 0 None None None None
0 1 C00h-FFFh 1800h-1FFFh 3000h-3FFFh 6000h-7FFFh
1 0 800h-FFFh 1000h-1FFFh 2000h-3FFFh 4000h-7FFFh
1 1 000h-FFFh 0000h-1FFFh 0000h-3FFFh 0000h-7FFFh
○WPB pin
By setting WPB=LOW, write command is prohibited. And the write command to be disabled at this moment is WRSR.
However, when write cycle is in execution, no interruption can be made.
Product number WRSR WRITE
BR25S320-W
Prohibition possible
but WPEN bit “1”
Prohibition
impossible
BR25S640-W
BR25S128-W
BR25S256-W
○HOLDB pin
By HOLDB pin, data transfer can be interrupted. When SCK=”0”, by making HOLDB from “1” into”0”, data transfer to
EEPROM is interrupted. When SCK = “0”, by making HOLDB from “0” into “1”, data transfer is restarted.