Datasheet

Version 20.00, July 2019
18 Rohde & Schwarz R&S
®
RTE Oscilloscope
Options
R&S
®
RTE-B1
Mixed signal option, additional 16 logic channels
Vertical system
Input channels
16 logic channels (D0 to D15)
Arrangement of input channels
arranged in two logic probes with
8 channels each, assignment of the logic
probes to the channels (D0 to D7 or D8 to
D15) is displayed on the probe
Input impedance
100 kΩ ± 2 % || ~4 pF (meas.) at probe
tips
Maximum input frequency
signal with minimum input voltage swing
and hysteresis setting: normal
400 MHz (meas.)
Maximum input voltage
±40 V (V
p
)
Minimum input voltage swing
500 mV (V
pp
) (meas.)
Threshold groups
D0 to D3, D4 to D7, D8 to D11 and D12 to
D15
Threshold level
range
±8 V in 25 mV steps
predefined
CMOS 5.0 V, CMOS 3.3 V, CMOS 2.5 V,
TTL, ECL, PECL, LVPECL
Threshold accuracy
±(100 mV + 3 % of threshold setting)
Comparator hysteresis
normal, robust, maximum
Horizontal system
Channel deskew
range for each channel
±200 ns
Channel-to-channel skew
< 500 ps (meas.)
Acquisition system
Sampling rate
max.
5 Gsample/s on each channel
Realtime waveform acquisition rate
max.
> 200 000 waveforms/s
Memory depth
100 Msample for every channel
Decimation
pulses lost due to decimation are
displayed
Trigger system
Holdoff range
time
100 ns to 10 s, fixed and random
events
1 event to 2 000 000 000 events
Trigger modes
Edge
triggers on specified slope (positive, negative or either) in the source signal
sources
any channel from D0 to D15 or any logical
combination of D0 to D15
Width
triggers on positive or negative pulse of specified width in the source signal; width can
be shorter, longer, equal, inside or outside the interval
sources
any channel from D0 to D15 or any logical
combination of D0 to D15
pulse width
200 ps to 10 s
Timeout
triggers when the source signal stays high, low or unchanged for a specified period of
time
sources
any channel from D0 to D15 or any logical
combination of D0 to D15
timeout
200 ps to 10 s
Data2clock
triggers on setup time and hold time violations between a clock signal and a data
signal; monitored time interval with a max. width of 200 ns and a position of
max. ±1 µs relative to the clock edge
data signal
any subset of channels from D0 to D15 or
any user-defined bus signal
clock signal
any channel from D0 to D15