User Manual

Remote Control
R&S
®
FPC
322User Manual 1178.4130.02 ─ 05
17.17.1 Structure of a SCPI Status Register
Each standard SCPI register contains 5 parts each of which have a width of 16 bits
and have different functions. The individual bits are independent of each other, that
means each hardware status is assigned a bit number that applies to all five parts. For
example, bit 9 of the STATus:QUEStionable register is assigned to the power char-
acteristics of the R&S FPC. Bit 15 (the most significant bit) is set to zero for all parts.
Thus the contents of the register parts can be processed by the controller as positive
integer.
CONDition part12131415 3 2 1 0
PTRansition part12131415 3 2 1 0
NTRansition part12131415 3 2 1 0
EVENt part12131415 3 2 1 0
ENABle part12131415 3 2 1 0
& & & & & & & & & & & & & &
+
Sum bit
to higher order register
& = logical AND
+ = logical OR
of all bits
Figure 17-5: Model of the status register
CONDition part
The CONDition part is directly written into by the hardware or the sum bit of the next
lower register. Its contents reflects the current instrument status. This register part can
only be read, but not written into or cleared. Its contents is not affected by reading.
PTRansition part
The Positive-TRansition (PTR) part acts as an edge detector. When a bit of the
CONDition part is changed from 0 to 1, the associated PTR bit decides whether the
EVENt bit is set to 1.
PTR bit = 1: the EVENt bit is set.
PTR bit = 0: the EVENt bit is not set.
This part can be written into and read at will. Its contents is not affected by reading.
NTRansition part
The Negative-TRansition (NTR) part also acts as an edge detector. When a bit of
the CONDition part is changed from 1 to 0, the associated NTR bit decides whether
the EVENt bit is set to 1.
NTR-Bit = 1: the EVENt bit is set.
NTR-Bit = 0: the EVENt bit is not set.
This part can be written into and read at will. Its contents is not affected by reading.
Status Reporting System