SLC 500 Instruction Set Catalog Numbers 1747-L20x, 1747-L30x, 1747-L40x, 1747-L511, 1747-L514, 1747-L524, 1747-L531, 1747-L532, 1747-L533, 1747-L541, 1747-L542, 1747-L543, 1747-L551, 1747-L552, 1747-L553 Reference Manual
Important User Information Solid state equipment has operational characteristics differing from those of electromechanical equipment. Safety Guidelines for the Application, Installation and Maintenance of Solid State Controls, publication SGI-1.1, available from your local Rockwell Automation sales office or online at http://www.literature.rockwellautomation.com), describes some important differences between solid state equipment and hard-wired electromechanical devices.
Summary of Changes The information below summarizes the changes to this manual since the last printing. To help you find new and updated information in this release of the manual, we have included change bars as shown next to this paragraph. The table below lists the sections that document new features and additional or updated information about existing features. 1 For This Information See Page Addition of a powerup error to Table 16.1.
2 Summary of Changes Notes: Publication 1747-RM001G-EN-P - November 2008
Table of Contents Preface Who Should Use This Manual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Purpose of This Manual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Related Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Common Techniques Used in This Manual . . . . . . . . . . . . . . . . . . . . P-1 P-1 P-2 P-2 Chapter 1 Processor Files File Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ii Table of Contents High-speed Counter Operation . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 Reset (RES). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Chapter 3 Comparison Instructions About the Comparison Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . Comparison Instructions Overview . . . . . . . . . . . . . . . . . . . . . . . . . . Using Indexed Word Addresses . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents iii Updates to Arithmetic Status Bits. . . . . . . . . . . . . . . . . . . . . . . . Square Root (SQR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Updates to Arithmetic Status Bits. . . . . . . . . . . . . . . . . . . . . . . . Scale with Parameters (SCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Updates to Arithmetic Status Bits. . . . . . . . . .
iv Table of Contents Chapter 5 Data Handling Instructions Publication 1747-RM001G-EN-P - November 2008 Convert to BCD (TOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Updates to Arithmetic Status Bits. . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Updates to the Math Register, S:13 and S:14 . . . . . . . . . . . . . . . . 5-3 Convert from BCD (FRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 Updates to Arithmetic Status Bits. . . . . . . . .
Table of Contents Effects on Index Register S:24 . . . . . . . . . . . . . . . . . . . . . . . . . . FIFO Load (FFL) and FIFO Unload (FFU) . . . . . . . . . . . . . . . . . . FFL Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FFU Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LIFO Load (LFL) and LIFO Unload (LFU) . . . . . . . . . . . . . . . . . . LFL Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi Table of Contents Sequencer Output (SQO) Sequencer Compare (SQC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 Enter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 Use SQO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 Use SQC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 Sequencer Load (SQL). . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents vii Scaled Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 Auto / Manual (AM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 Control (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 Deadband (DB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 Reset and Gain Enhancement Bit (RG) . . . . . . . . . . . . . . . . . . .
viii Table of Contents Number of ASCII Characters In Buffer (ACB) . . . . . . . . . . . . . . . . 10-7 Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 String to Integer (ACI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 ASCII Clear Receive and/or Transmit Buffer (ACL) . . . . . . . . . . . 10-9 Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 String Concatenate (ACN). . . . . . . . . . .
Table of Contents STD/STE Zone Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selectable Timed Start (STS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Discrete Input Interrupt Overview . . . . . . . . . . . . . . . . . . . . . . . . . Basic Programming Procedure for the DII Function . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
x Table of Contents Rung Goes True. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Next End of Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Successful Receipt of Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . An ACK is Not Received . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Target Node Sends a Reply Packet . . . . . . . . . . . . . . . . . . . . . . MSG Instruction Error Codes. . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents xi DF1 Half-duplex Communications. . . . . . . . . . . . . . . . . . . . . . . . . 13-55 DF1 Half-duplex Master Broadcast . . . . . . . . . . . . . . . . . . . . . 13-55 DF1 Half-duplex Slave Broadcast. . . . . . . . . . . . . . . . . . . . . . . 13-55 Configuring Channel 0 for Standard Polling Mode DF1 Half-duplex Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xii Table of Contents Using RSLinx Classic, version 2.50 and higher, with SLC 5/03 Passthru . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 SLC 5/03 Passthru Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . 14-7 Using RSLinx Classic, version 2.50 and higher, with SLC 5/04 Passthru . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8 Creating and Filling out the Passthru Routing Table File . . . . .
Table of Contents Network Message Example: SLC 5/04 to SLC 5/03 via KA5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Network Message Example: SLC 5/04 to SLC 5/05 via DHRIO and ENET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Network Message Example: SLC 5/05 to SLC 5/04 via ENET and DHRIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Network Message Example: SLC 5/05 to SLC 5/03 via ENET, CNB and KFC . . . . . . . . . . . . . . . . .
xiv Table of Contents OS400, Series A, FRN 1 released: August 1994. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Original Release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OS301, Series A, FRN 6 OS400, Series A, FRN 2 released: November 1994. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents xv OS302, Series B, FRN 12 released: November 1998 OS401, Series B, FRN 9 released: July 1999 OS501, Series A, FRN 4 released: February 1999 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6 Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6 OS302, Series B, FRN 14 OS401, Series B, FRN 9 released: July 1999 OS501, Series A, FRN 4 released: February, 1999. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xvi Table of Contents OS302, Series C, FRN 8 OS401, Series C, FRN 8 OS501, Series C, FRN 8 released: May 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OS501, Series C, FRN 9 released: November 2004. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents xvii Appendix D Programming Instruction References Valid Addressing Modes and File Types. . . . . . . . . . . . . . . . . . . . . . D-1 Understanding the Different Addressing Modes . . . . . . . . . . . . D-2 Appendix E Data File Organization and Addressing Understanding File Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1 Processor File Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1 Addressing Data Files . . . . . . . . . . . . .
xviii Table of Contents On/Off Circuit Application Example. . . . . . . . . . . . . . . . . . . . . . . On/Off Circuit Ladder Program. . . . . . . . . . . . . . . . . . . . . . . . . . . Interfacing with Enhanced Bar Code Decoders Over DH-485 Network Using the MSG Instruction . . . . . . . . . . . . . . . . . . . . . . . Processor and Decoder Operation . . . . . . . . . . . . . . . . . . . . . . System Set Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Sequence .
Preface Read this preface to familiarize yourself with the rest of the manual. It provides information concerning: • • • • Who Should Use This Manual who should use this manual. the purpose of this manual. related documentation. common techniques used in this manual Use this manual if you are responsible for designing, installing, programming, or troubleshooting control systems that use SLC 500 programmable controllers.
2 Preface Related Documentation The following documents contain additional information concerning Rockwell Automation products. To obtain a copy, contact your local Rockwell Automation office or distributor. For Read This Document Document Number An overview of the SLC 500 family of products. SLC 500 System Overview 1747-SO001 A description on how to install and use your Modular SLC 500 programmable controller.
Chapter 1 Processor Files File Structure SLC 500 user memory is comprised of Data Files and Program Files. TIP The file types shown below for data files 3 through 8 are the default values. Files 9 to 255 can be configured to be bit, timer, counter, control, integer, floating point, ASCII, or String files.
1-2 Processor Files Output and Input Data Files (Files O0: and I1:) Data Files 0 and 1 represent external outputs and inputs, respectively. Bits in file 1 are used to represent external inputs. In most cases, a single 16-bit word in these files will correspond to a slot location in your controller, with bit numbers corresponding to input or output terminal numbers. Unused bits of the word are not available for use. Table 1.1 explains the addressing format for outputs and inputs.
Processor Files 1-3 Status File (File S2:) You cannot add to or delete from the status file. See Table 1.2 to understand how to address various bits and words within the status file. You can address various bits and words as follows. Table 1.
1-4 Processor Files Table 1.3 Bit File Addressing Format Format Explanation Bf:e/b B Bit type file f File number. Number 3 is the default file. A file number between 9-255 can be used if additional storage is required. : Element delimiter e Element number / Bit delimiter b Bit number B f / Same as above. Same as above. Same as above. b Bit number Bf/b Ranges from 0-255. These are 1-word elements. 16 bits per element. Bit location within the element. Ranges from 0-15.
Processor Files 1-5 Table 1.4 Timer Control Fields 15 14 13 EN TT DN 12 11 10 9 8 7 6 5 4 3 2 1 0 Word 0 Internal Use(1) Preset Value (PRE) 1 Accumulator Value (ACC) 2 (1) Bits labeled “Internal Use” are not addressable. Table 1.5 Timer Elements Addressable Bits Addressable Words EN = Enable (Bit 15) PRE = Preset Value TT = Timer Timing (Bit 14) ACC = Accumulated Value DN = Done (Bit 13) Addressing Structure Address bits and words using the format Tf:e.s/b. Table 1.
1-6 Processor Files Counter Data File Elements (C5:) Each Counter address is made of a 3-word data file element. Word 0 is the control word, containing the status bits of the instruction. Word 1 is the preset value. Word 2 is the accumulated value. The control word for counter instructions includes five status bits, as indicated below. Table 1.
Processor Files 1-7 Entering Parameters There are several parameters associated with Counter instructions. The following parameters detail the operations of the counter. Accumulator Value (ACC) This is the number of false-to-true transitions that have occurred since the counter was last reset. Preset Value (PRE) Specifies the value which the counter must reach before the controller sets the done bit (DN).
1-8 Processor Files Table 1.9 Counter File Addressing Format Explanation C5:0/11 or C5:0/UN Underflow bit C5:0/10 or C5:0/UA Update accum. bit (use with HSC in fixed controller only) C5:0.1 or C5:0.PRE Preset value of the counter C5:0.2 or C5:0.ACC Accumulated value of the counter C5:0.1/0 or C5:0.PRE/0 Bit 0 of the preset value C5:0.2/0 or C5:0.ACC/0 Bit 0 of the accumulated value Control Data File (R6:) These instructions use various control bits.
Processor Files 1-9 Table 1.11 Control Elements DN = Done EM = Stack Empty ER = Error UL = Unload IN = Inhibit FD = Found Assign control addresses as follows. Table 1.12 Control File Addressing Format Format Rf:e Rf:e.s/b Explanation R Control file f File number. Number 6 is the default file. A file number between 9 and 255 can be used if additional storage is required. : Element delimiter e Element number Rf:e Explained above. .
1-10 Processor Files Integer Data File (N7:) Use these addresses as your program requires. These are 1-word elements, addressable at the element and bit level. Assign integer addresses as follows. Table 1.13 Integer File Addressing Format Format Nf:e/b Explanation N Integer file f File number. Number 7 is the default file. A file number between 9 to255 can be used if additional storage is required. : Element delimiter e Element number / Bit delimiter b Bit number Ranges from 0 to 255.
Processor Files 1-11 Float Data File (F8:) Use these addresses as your program requires. These are 2-word elements, addressable at the element and bit level. Assign float addresses as follows. Table 1.14 Float File Addressing Format Format Ff:e Explanation F Integer file f File number. Number 8 is the default file. A file number between 9 to 255 can be used if additional storage is required. : Element delimiter e Element number Ranges from 0 to 255. These are 2-word elements.
1-12 Processor Files Notes: Publication 1747-RM001G-EN-P - November 2008
Chapter 2 Basic Instructions This chapter contains general information about the basic instructions and explains how they function in your application program. Each of the basic instructions includes information on: • the instruction symbol. • the instruction format. • the instruction usage. The Basic Instructions detailed in this chapter are listed in Table 2.1. Table 2.
2-2 Basic Instructions About the Basic Instructions Basic instructions, when used in ladder programs, represent hardwired logic circuits used for the control of a machine or equipment. The basic instructions are separated into three groups: bit, timer, and counter. Before you learn about the instructions in each of these groups, we suggest that you read the overviews that follow: • Bit Instructions Overview. • Timer Instructions Overview. • Counter Instructions Overview.
Basic Instructions 2-3 Use the XIC instruction in your ladder program to determine if a bit is On. When the instruction is executed, if the bit addressed is on (1), then the instruction is evaluated as true. When the instruction is executed, if the bit addressed is off (0), then the instruction is evaluated as false. Examine if Closed (XIC) Table 2.
2-4 Basic Instructions Use the OTE instruction in your ladder program to turn on a bit when rung conditions are evaluated as true. Output Energize (OTE) An example of a device that turns on or off is an output wired to a pilot light (addressed as O:0/4). ( ) OTE instructions are reset when: Fixed SLC SLC SLC SLC SLC 5/01 5/02 5/03 5/04 5/05 • • • • • • Output Instruction • the SLC enters or returns to the REM Run or REM Test mode or power is restored.
Basic Instructions 2-5 When enabled, the latch instruction tells the controller to turn on the addressed bit. Thereafter, the bit remains on, regardless of the rung condition, until the bit is turned off (typically by a OTU instruction in another rung). Using OTU When you assign an address to the OTU instruction that corresponds to the address of a physical output, the output device wired to this screw terminal is de-energized when the bit is cleared (turned off or disabled).
2-6 Basic Instructions TIP The bit address you use for this instruction must be unique. Do not use it elsewhere in the program. Do not use an input or output address to program the address parameter of the OSR instruction. Examples The following rungs illustrate the use of the OSR instruction. The first four rungs apply to SLC 500 and SLC 5/01 processors. The fifth rung involves output branching and applies to the SLC 5/02 and higher processors. SLC 500 and SLC 5/01 Processors O:3.0 I:1.
Basic Instructions 2-7 The SLC 500 and SLC 5/01 processors allow you to use only one OSR instruction per rung. ATTENTION When using a SLC 500 or SLC 5/01 processor, do not place input conditions after the OSR instruction in a rung. Unexpected operation may occur. SLC 5/02 (and higher) Processors I:1.0 ] [ 0 B3 ]/[ 1 B3 O:3.0 B3 [OSR] ] [ ( ) 0 0 4 B3 ] [ 2 B3 [OSR] 3 B3 O:3.0 ]/[ ( ) 5 1 The SLC 5/02 and higher processors allow you to use one OSR instruction per output in a rung.
2-8 Basic Instructions Timebase The timebase determines the duration of each timebase interval. For Fixed and SLC 5/01 processors, the timebase is set at 0.01 second. EXAMPLE If the timer base is set to 0.01, it would take 100 counts as the preset value (PRE) to equal 1 seconds worth of timing. Timer Accuracy Timer accuracy refers to the length of time between the moment a timer instruction is enabled and the moment the timed interval is complete.
Basic Instructions 2-9 Use the TON instruction to turn an output on or off after the timer has been on for a preset time interval. The TON instruction begins to count timebase intervals when rung conditions become true. As long as rung conditions remain true, the timer adjusts its accumulated value (ACC) each evaluation until it reaches the preset value (PRE). The accumulated value is reset when rung conditions go false, regardless of whether the timer has timed out.
2-10 Basic Instructions Use the TOF instruction to turn an output on or off after its rung has been off for a preset time interval. The TOF instruction begins to count timebase intervals when the rung makes a true-to-false transition. As long as rung conditions remain false, the timer increments its accumulated value (ACC) based on the timebase for each scan until it reaches the preset value (PRE). The accumulated value is reset when rung conditions go true regardless of whether the timer has timed out.
Basic Instructions ATTENTION TIP • • (EN) (DN) • The TOF timer times inside an inactive MCR Pair. The RTO instruction retains its accumulated value when any of the following occurs. Fixed SLC SLC SLC SLC SLC 5/01 5/02 5/03 5/04 5/05 • The Reset (RES) instruction cannot be used with the TOF instruction because RES always clears the status bits as well as the accumulated value. (See 2-20) Use the RTO instruction to turn an output on or off after its timer has been on for a preset time interval.
2-12 Basic Instructions Using Status Bits Table 2.
Basic Instructions Counter Instructions Overview 2-13 How Counters Work The figure below demonstrates how a counter works. The count value must remain in the range of − 32768 to + 32767. If the count value goes above + 32767 or below − 32768, the counter status overflow (OV) or underflow (UN) bit is set. A counter can be reset to zero using the reset (RES) instruction.
2-14 Basic Instructions Using Status Bits Table 2.
Basic Instructions 2-15 Using Status Bits Table 2.11 Setting CTD Status Bits This Bit Is Set When And Remains Set Until One of the Following Count Down Underflow Bit UN (Bit 11) accumulated value wraps around to +32,767 (from -32,768) and continues counting down from there a RES instruction having the same address as the CTD instruction is enabled.
2-16 Basic Instructions This instruction provides high-speed counting for fixed I/O controllers with 24 VDC inputs. One HSC instruction is allowed per controller. To use the instruction, you must cut the jumper as shown below. A shielded cable is recommended to reduce noise to the input. High-speed Counter Data Elements Address C5:0 is the HSC counter 3-word element. Table 2.
Basic Instructions 2-17 High-speed Counter Operation For high-speed counter operation you must: 1. Turn off power to the fixed controller. 2. Remove the SLC 500 cover. 3. Locate and cut jumper wire J2. Do not remove completely but make certain that the ends of the cut jumper wire are not touching each other. The High-speed Counter jumper is located either beneath the battery connector OR to the right of the battery connector. 4. Replace the cover. Input I:0/0 then operates in the high-speed mode.
2-18 Basic Instructions The HSC differs from the CTU and CTD counters. The CTU and CTD are software counters. The HSC is a hardware counter and operates asynchronously to the ladder program scan. The HSC accumulated value (C5:0.ACC) is normally updated each time the HSC rung is evaluated in the ladder program. This means that the HSC hardware accumulator value is transferred to the HSC software accumulator. Only use the OTE instruction to transfer this value.
Basic Instructions 2-19 Application Example - File 2 (Poll for DN Bit in Main Program) JSR Rung 1 C5:0 ] [ DN Rung 2 ] [ ] [ ] [ ( ) ] [ ] [ ( ) JUMP TO SUBROUTINE • • • Rung 17 ] [ Rung 18 C5:0 ] [ DN Rung 19 ] [ ] [ ] [ ( ) ] [ ] [ ( ) • • • Rung 30 ] [ Rung 31 C5:0 ] [ DN Rung 32 ] [ 3 JSR JUMP TO SUBROUTINE 3 JSR JUMP TO SUBROUTINE ( ) ] [ ] [ 3 Application Example - File 3 (Execute HSC Logic) Rung 0 ] [ Rung 1 ] [ ( ) ] [ Application Logic ( )
2-20 Basic Instructions Use a RES instruction to reset a timer or counter. When the RES instruction is enabled, it resets the Timer On Delay (TON), Retentive Timer (RTO), Count Up (CTU), or Count Down (CTD) instruction having the same address as the RES instruction. Reset (RES) Table 2.13 Using an RES Instruction (RES) Fixed SLC SLC SLC SLC SLC 5/01 5/02 5/03 5/04 5/05 • • • • • Using a RES instruction for a: The processor resets the: Timer (Do not use a RES instruction with a TOF.
Chapter 3 Comparison Instructions This chapter contains general information about comparison instructions and explains how they function in your application program. Each of the comparison instructions includes information on: • the instruction symbol. • instruction usage. Table 3.
3-2 Comparison Instructions Comparison Instructions Overview The following general information applies to comparison instructions. Using Indexed Word Addresses When using comparison instructions, you have the option of using indexed word addresses for instruction parameters specifying word addresses.
Comparison Instructions Less Than (LES) Use the LES instruction to test whether one value (source A) is less than another (source B). If source A is less than the value at source B, the instruction is logically true. If the value at source A is greater than or equal to the value at source B, the instruction is logically false. LES Less Than (A
3-4 Comparison Instructions Greater Than or Equal (GEQ) GEQ Grtr Than or Eql (A>=B) Source A N7:10 0< Source B N7:11 0< Fixed SLC SLC SLC SLC SLC 5/01 5/02 5/03 5/04 5/05 • • • • • Use the GEQ instruction to test whether one value (source A) is greater than or equal to another (source B). If the value at source A is greater than or equal to the value at source B, the instruction is logically true. If the value at source A is less than the value at source B, the instruction is logically false.
Comparison Instructions Limit Test (LIM) LIM Limit Test Low Lim Test High Lim Use the LIM instruction to test for values within or outside a specified range, depending on how you set the limits.
3-6 Comparison Instructions Notes: Publication 1747-RM001G-EN-P - November 2008
Chapter 4 Math Instructions This chapter contains general information about math instructions and explains how they function in your logic program. Each of the math instructions includes information on: • instruction symbol. • instruction usage. Table 4.1 Math Instructions Instruction Mnemonic ADD SUB MUL DIV DDV CLR SQR SCP SCL RMP ABS CPT SWP ASN ACS ATN COS LN LOG SIN TAN XPY 1 Purpose Name Add Subtract Multiply Divide Page Adds source A to source B and stores the result in the destination.
4-2 Math Instructions About the Math Instructions The majority of the instructions take two input values, perform the specified arithmetic function, and output the result to an assigned memory location. For example, both the ADD and SUB instructions take a pair of input values, add or subtract them, and place the result in the specified destination. If the result of the operation exceeds the allowable value, an overflow or underflow bit is set.
Math Instructions 4-3 Updates to Arithmetic Status Bits The arithmetic status bits are found in Word 0, bits 0 to 3 in the controller status file. After an instruction is executed, the arithmetic status bits in the status file are updated. Table 4.2 Processor Function With this Bit The Controller S:0/0 Carry (C) sets if carry is generated; otherwise cleared. S:0/1 Overflow (V) indicates that the actual result of a math instruction does not fit in the designated destination.
4-4 Math Instructions Using Floating Point Data File (F8:) This file type is valid for SLC 5/03 (OS301 and higher), SLC 5/04, and SLC 5/05 processors. These are 2-word elements and addressable only at the element level. Assign floating point addresses as follows. Table 4.3 Addressing Format Format Ff:e Explanation F f : e Examples: Publication 1747-RM001G-EN-P - November 2008 F8:2 F10:36 Floating Point file File number. Number 8 is the default file.
Math Instructions 4-5 Use the ADD instruction to add one value (source A) to another value (source B) and place the result in the destination. Add (ADD) Updates to Arithmetic Status Bits ADD Add Source A N7:14 6< N7:15 8< N7:16 0< Source B Dest The arithmetic status bits are found in Word 0, bits 0 to 3 in the status file. After an instruction is executed, the arithmetic status bits in the status file are updated. Fixed SLC SLC SLC SLC SLC 5/01 5/02 5/03 5/04 5/05 • • • • • • Table 4.
4-6 Math Instructions You have the option of performing 16-bit or 32-bit signed integer addition and subtraction. This is facilitated by status file bit S:2/14 (math overflow selection bit). 32-Bit Addition and Subtraction Math Overflow Selection Bit S:2/14 Fixed SLC SLC SLC SLC SLC 5/01 5/02 5/03 5/04 5/05 • • • • Set this bit when you intend to use 32-bit addition and subtraction.
Math Instructions 4-7 Example of 32-bit Addition The following example shows how a 16-bit signed integer is added to a 32-bit signed integer. Remember that S:2/14 must be set for 32-bit addition. Note that the value of the most significant 16 bits (B3:3) of the 32-bit number is increased by 1 if the carry bit S:0/0 is set and it is decreased by 1 if the number being added (B3:1) is negative. The largest possible number is 2,147,483,647 (7FFF FFFF)h.
4-8 Math Instructions B3 ] [ 0 When rung goes true for a single scan, B3:1 is added to B3:2. The result is placed in B3:2 ADD B3 [OSR] 1 ADD Source A B3:1 0101010110101000 Source B B3:2 0001100101000000 Dest B3:2 0001100101000000 S:0 ] [ 0 If a carry is generated (S:0/0 set), 1 is added to B3:3. ADD ADD Source A 1 Source B B3:3 0000000000000011 Dest B3:3 0000000000000011 B3 ] [ 31 SUB SUBTRACT Source A B3:3 0000000000000011 Source B 1 If B3:1 is negative (B3/31 set), 1 is subtracted from B3:3.
Math Instructions 4-9 Table 4.7 Processor Function With this Bit The Processor S:0/0 Carry (C) always resets. S:0/1 Overflow (V) sets if overflow is detected at destination; otherwise resets. On overflow, the minor error flag is also set. The value -32,768 or 32,767 is placed in the destination.
4-10 Math Instructions Table 4.8 Processor Function With this Bit The Processor S:0/0 Carry (C) always resets. S:0/1 Overflow (V) sets if division by zero or overflow is detected; otherwise resets. On overflow, the minor error flag is also set. The value 32,767 is placed in the destination. Exception: If you are using an SLC1 5/02 or higher processor and have S:2/14 (math overflow selection bit) set, then the unsigned, truncated overflow remains in the destination.
Math Instructions 4-11 The 32-bit content of the math register is divided by the 16-bit source value and the rounded quotient is placed in the destination. If the remainder is 0.5 or greater, the destination is rounded up. Double Divide (DDV) DDV Double Divide Source N7:26 0< Dest N7:27 0< This instruction typically follows a MUL instruction that creates a 32-bit result.
4-12 Math Instructions Use the CLR instruction to set the destination value of a word to zero. Clear (CLR) Updates to Arithmetic Status Bits CLR Clear Dest N7:27 0< Fixed SLC SLC SLC SLC SLC 5/01 5/02 5/03 5/04 5/05 • • • • • • Output Instruction With this Bit The Processor S:0/0 Carry (C) always resets. S:0/1 Overflow (V) always resets. S:0/2 Zero (Z) always sets. S:0/3 Sign (S) always resets.
Math Instructions 4-13 Use the SCP instruction to produce a scaled output value that has a linear relationship between the input and scaled values. This instruction supports integer and floating point values. Use this instruction with SLC 5/03 (OS302), SLC 5/04 (OS401), and SLC 5/05 processors. Scale with Parameters (SCP) Use the following formula to convert analog input data to engineering units. SCP Scale w/Parameters Input N7:30 100< Input Min. 0 0< Input Max. 32767 32767< Scaled Min.
4-14 Math Instructions Updates to Arithmetic Status Bits The arithmetic status bits are found in Word 0, bits 0 to 3 in the status file. After an instruction is executed, the arithmetic status bits in the status file are updated. Table 4.12 Processor Function With this Bit The Processor S:0/0 Carry (C) always resets. S:0/1 Overflow (V) sets if overflow generated or an unsupported input is detected; otherwise resets. S:0/2 Zero (Z) sets when destination value is zero; otherwise resets.
Math Instructions 4-15 Example 2 In the second example, an analog I/O combination module (1746-NIO4I) is in slot 1 of the chassis. We want to control the proportional valve connected to output 0. The valve takes a 4 to 20 mA signal to control how far it opens (0 to 100%). (Assume that additional logic is present in the program that calculates how far to open the valve in percent and places a number between 0 and 100 into N7:21.
4-16 Math Instructions TIP Anytime an underflow or overflow occurs in the destination file, minor error bit S:5/0 must be reset by the program. This must occur before the end of the current scan to prevent major error code 0020 from being declared. This instruction can overflow before the offset is added. Note that the term rate is sometimes referred to as slope. The rate function is limited to the range -3.2768 to 3.2767. For example, -32768/10000 to +32767/10000.
Math Instructions 4-17 Application Example 1 - Converting 4 to 20 mA Analog Input Signal to PID Process Variable 16,383 (Scaled MAX.) Scaled Value 0 (Scaled MIN.) 3,277 (Input MIN.) Input Value 16,384 (Input MAX.) Calculating the Linear Relationship Use the following equations to express the linear relationship between the input value and the resulting scaled value. Scaled value = (Input Value X Rate) + Offset Rate = (Scaled MAX. - Scaled MIN.) / (Input MAX. - Input MIN.
4-18 Math Instructions Application Example 2 - Scaling an Analog Input to Control an Analog Output 32,764 10V (Scaled MAX.) Scaled Value 0 0V (Scaled MIN.) 3,277 4 mA (Input MIN.) 16,384 20 mA (Input MAX.) Input Value Calculating the Linear Relationship Use the following equations to calculate the scaled units. Scaled value = (Input Value X Rate) + Offset Rate = (Scaled MAX. - Scaled MIN.) / (Input MAX. - Input MIN.) (32,764 - 0) / (16,384 - 3277) = 2.4997 (or 24,997/10000) Offset = Scaled MIN.
Math Instructions 4-19 Notice that an overflow occurred even though the final value was correct. This happens because the overflow condition occurred during the rate calculation. The following graph shows the shifted linear relationship. The input minimum value of 3,277 is subtracted from the input maximum value of 16,384, resulting in the value of 13,107. 32,764 10V (Scaled MAX.) Scaled Value 0 0V (Scaled MIN.) 0 4 mA (Shifted Input MIN.) 13,107 20 mA (Shifted Input MAX.
4-20 Math Instructions In this example, the SCL instruction is entered in the ladder logic program as follows. Apply the Shift SUB SUBTRACT Source A Source B Dest Analog Input I:1.0 3277 N7:0 Scale Shifted Analog Value SCL SCALE Source Rate [/10000] Offset Dest N7:0 24997 0 O:2.0 Analog Output The Ramp (RMP) instruction provides the ability to create linear, acceleration, deceleration, and “S” curve ramp output data wave forms.
Math Instructions 4-21 Table 4.14 Ramp Instruction Control Structure Word 0 15 14 13 12 EN RMP DN ER 11 10 9 8 7 Desired Time Word 2 Current Time Word 3 Beginning Output Value Word 4 Ending Output Value Words 5 and 6 Internal use only (1) TB = 0, Timebase = 0.01 seconds TB = 1, Timebase = 1.
4-22 Math Instructions Instruction Operation When the rung state is true all parameters are validated to be in range. If the parameters are valid, the ramp function places the calculated output value in the destination register. The parameters are validated for every scan when the rung state is true. When the Ramp instruction is scanned and the rung state is true, the current time is updated, the destination value is calculated, and done condition is checked.
Math Instructions 4-23 RMP Equation The Ramp instruction is defined based on the following equations.
4-24 Math Instructions Use the ABS instruction to calculate the absolute value of the Source and place the result in the Destination. This instruction supports integer and floating point values. Use this instruction with SLC 5/03 (OS302), SLC 5/04 (OS401), and SLC 5/05 processors. Absolute (ABS) Entering Parameters ABS Absolute Value Source N7:34 0< Dest N7:35 0< Enter the following parameters when programming this instruction.
Math Instructions The CPT instruction performs copy, arithmetic, logical, and conversion operations. You define the operation in the Expression and the result is written in the Destination. The CPT uses functions to operate on one or more values in the Expression to perform operations such as: Compute (CPT) CPT Compute Dest Expression 4-25 N7:36 3< ( N7:13 AND N7:14 ) OR N7:15 • converting from one number format to another. • manipulating numbers. • performing trigonometric functions.
4-26 Math Instructions Updates to Arithmetic Status Bits The arithmetic status bits are found in Word 0, bits 0 to 3 in the status file. After an instruction is executed, the arithmetic status bits in the status file are updated. Table 4.16 Processor Function With this Bit The Processor S:0/0 Carry (C) sets based on the result of the last instruction in the Expression. S:0/1 Overflow (V) sets any time an overflow occurs during the evaluation of the Expression.
Math Instructions 4-27 Rung 2:0 uses standard math instructions to implement Pythagorean’s theorem. Rung 2:1 uses the CPT instruction to obtain the same calculation.
4-28 Math Instructions Use this instruction to swap the low and high bytes of a specified number of words in a bit, integer, ASCII, or string file. Use this instruction with SLC 5/03 (OS302), SLC 5/04 (OS401), and SLC 5/05 processors. Swap (SWP) Entering Parameters SWP Swap Source #ST10:1.DATA[0] Length 5 Enter the following parameters when programming this instruction.
Math Instructions 4-29 Use the ASN instruction to take the arc sine of a number and store the result (in radians) in the destination. The source must be greater than or equal to -1 and less than or equal to 1. The resulting value in the destination is always greater than or equal to -Pi/2 and less than or equal to Pi/2, where Pi = 3.141592. Use this instruction with SLC 5/03 (OS302), SLC 5/04 (OS401), and SLC 5/05 processors.
4-30 Math Instructions Use the ATN instruction to take the arc tangent of a number (source) and store the result (in radians) in the destination. The resulting value in the destination is always greater than or equal to -Pi/2 and less than or equal to Pi/2, where Pi = 3.141592. Use this instruction with SLC 5/03 (OS302), SLC 5/04 (OS401), and SLC 5/05 processors.
Math Instructions 4-31 Use the LN instruction to take the natural log of the value in the source and store the result in the destination. The source must be greater than zero. The resulting value in the destination is always greater than or equal to -87.33654 and less than or equal to 88.72284. Use this instruction with SLC 5/03 (OS302), SLC 5/04 (OS401), and SLC 5/05 processors.
4-32 Math Instructions Use the SIN instruction to take the sine of a number (source in radians) and store the result in the destination. The source must be greater than or equal to -205887.4 and less than or equal to 205887.4. The greatest accuracy is achieved when the source is greater than -2 Pi and less than 2 Pi, where Pi = 3.141592. The resulting value in the destination is always greater than or equal to -1 and less than or equal to 1.
Math Instructions X to the Power of Y (XPY) 4-33 Use the XPY instruction to raise a value (source A) to a power (source B) and store the result in the destination. If the value in source A is negative, the exponent (source B) should be a whole number. If it is not a whole number, the overflow bit is set and the absolute value of the base is used in the calculation. Use this instruction with SLC 5/03 (OS302), SLC 5/04 (OS401), and SLC 5/05 processors. The XPY instruction uses the following algorithm.
4-34 Math Instructions Notes: Publication 1747-RM001G-EN-P - November 2008
Chapter 5 Data Handling Instructions This chapter contains general information about the data handling instructions and explains how they function in your application program. Each of the instructions includes information on: • what the instruction symbol looks like. • how to use the instruction. Table 5.
5-2 Data Handling Instructions Use this instruction to convert 16-bit integers into BCD values. Convert to BCD (TOD) TOD To BCD Source Dest With Fixed and SLC 5/01 processors, the destination can only be the math register. With SLC 5/02 and higher processors, the destination parameter can be a word address in any data file, or it can be the math register, S:13 and S:14.
Data Handling Instructions 5-3 Updates to the Math Register, S:13 and S:14 Contains the 5-digit BCD result of the conversion. This result is valid at overflow. Example 1 The integer value 9760 stored at N7:3 is converted to BCD and the BCD equivalent is stored in N10:0. The maximum BCD value possible is 9999. TOD TO BCD Source Dest The destination value is displayed in BCD format.
5-4 Data Handling Instructions 0 0 15 S:14 0 3 2 7 6 0 N7:3 Decimal 3 2 7 6 0 S:13 & S:14 5-digit BCD 0 15 0 S:13 This example will output the absolute value (0 to 32767) contained in N7:3 as 5 BCD digits in output slots 2 and 3. TOD ] [ TO BCD Source Dest N7:3 32760 S:13 00032760 S:13 and S:14 are displayed in BCD format. S:5 (U) 0 S:0 ] [ 1 Minor Error Bit MOV MOVE Source Dest S:13 10080 O:2.0 10080 0010 0111 0110 0000 MVM MASKED MOVE Source S:14 Mask 000F 3 Dest O:3.
Data Handling Instructions 5-5 Use this instruction to convert BCD values to integer values. With Fixed and SLC 5/01 processors, the source can only be the math register. With SLC 5/02 and higher processors, the source parameter can be a word address in any data file, or it can be the math register, S:13. Convert from BCD (FRD) Updates to Arithmetic Status Bits FRD From BCD Source N7:58 0156h< Dest N7:59 0< The arithmetic status bits are found in Word 0, bits 0 to 3 in the status file.
5-6 Data Handling Instructions To convert numbers larger than 9999 BCD, the source must be the Math Register (S:13). You must reset the Minor Error bit (S:5/0) to prevent an error. TIP Changes to the Math Register, S:13 and S:14 Used as the source for converting the entire number range of a register. Example 1 The BCD value 9760 at source N7:3 is converted and stored in N10:0. The maximum source value is 9999, BCD.
Data Handling Instructions 5-7 Example 2 The BCD value 32760 in the math register is converted and stored in N7:0. The maximum source value is 32767, BCD. FRD FROM BCD Source Dest S:14 0000 15 0 0000 0000 0011 0 0 0 3 3 S:13 00032760 N7:0 32760 S:13 and S:14 are displayed in BCD format. S:13 0010 0111 0110 0000 15 0 5-digit BCD 2 7 6 0 2 7 6 0 N7:0 Decimal 0111 1111 1111 1000 You should convert BCD values to integer before you manipulate them in your ladder program.
5-8 Data Handling Instructions Clearing S:14 before executing the FRD instruction is shown. I:1 ] [ 0 MOV MOVE Source N7:2 4660 S:13 4660 Dest 0001 0010 0011 0100 CLR CLEAR Dest S:14 0 FRD FROM BCD Source Dest S:13 00001234 N7:0 1234 S:13 and S:14 are displayed in BCD format. 0000 0100 1101 0010 When the input condition is set (1), a BCD value (transferred from a 4-digit thumb wheel switch for example) is moved from word N7:2 into the math register.
Data Handling Instructions 5-9 Updates to Arithmetic Status Bits The arithmetic status bits are found in Word 0, bits 0 to 3 in the status file. After an instruction is executed, the arithmetic status bits in the status file are updated. Table 5.4 Processor Function Degrees to Radians (RAD) S:0/0 Carry (C) always resets.
5-10 Data Handling Instructions Updates to Arithmetic Status Bits The arithmetic status bits are found in Word 0, bits 0 to 3 in the status file. After an instruction is executed, the arithmetic status bits in the status file are updated. Table 5.5 Processor Function With this Bit The Processor S:0/0 Carry (C) always resets.
Data Handling Instructions 5-11 Entering Parameters • Source is the address that contains the bit decode information. Only the first four bits (0 to 3) are used by the DCD instruction. The remaining bits may be used for other application specific needs. Change the value of the first four bits of this word to select one bit of the destination word. • Destination is the address of the word where the data is to be stored. Updates to Arithmetic Status Bits Unaffected.
5-12 Data Handling Instructions Entering Parameters • Source is the address of the word to be encoded. Only one bit of this word should be on at any time. If more than one bit in the source is set, the destination bits are set based on the least significant bit that is set. If a source of zero is used, all of the destination bits are reset and the arithmetic status zero bit (S:0/2) is set. • Destination is the address that contains the bit encode information.
Data Handling Instructions Copy File (COP) and Fill File (FLL) Instructions FLL Fill File Source 0 Dest #ST14:0 Length 3 Using COP Fixed SLC SLC SLC SLC SLC 5/01 5/02 5/03 5/04 5/05 • • The destination file type determines the number of words that an instruction transfers. For example, if the destination file type is a counter and the source file type is an integer, three integer words are transferred for each element in the counter-type file.
5-14 Data Handling Instructions All elements are copied from the source file into the destination file each time the instruction is executed. Elements are copied in ascending order. If your destination file type is a timer, counter, or control file, be sure that the source words corresponding to the status words of your destination file contains zeros. Be sure that you accurately specify the starting address and length of the data block you are copying.
Data Handling Instructions 5-15 Entering Parameters Enter the following parameters when programming this instruction. • Source is the program constant or element address. The file indicator (#) is not required for an element address. When using either an SLC 5/03 (OS301 or higher), SLC 5/04 (OS401), or SLC 5/05 processor, floating point and string values are supported. • Destination is the destination starting address of the file you want to fill. You must use the file indicator (#) in the address.
5-16 Data Handling Instructions Move and Logical Instructions Overview The following general information applies to move and logical instructions. Entering Parameters • Source is the address of the value on which the logical or move operation is to be performed. The source can be a word address or a program constant, unless otherwise described. If the instruction has two source operands, it does not accept program constants in both operands.
Data Handling Instructions 5-17 Updates to the Math Register, S:13 and S:14 Move and logical instructions do not affect the math register. Entering Mask Values TIP When entering constants, you can use ‘b’ or ‘h’ to change the radix of your entry. For example, instead of entering -1 as a constant, you could enter 1111111111111111b or FFFFh. This output instruction moves the source value to the destination location. As long as the rung remains true, the instruction moves the data each scan.
5-18 Data Handling Instructions Table 5.7 Controller Function With this Bit The Controller S:0/0 Carry (C) always resets. S:0/1 Overflow (V) always resets. S:0/2 Zero (Z) sets if result is zero; otherwise resets. S:0/3 Sign (S) sets if result is negative (most significant bit is set); otherwise resets. The MVM instruction is a word instruction that moves data from a source location to a destination, and allows portions of the destination data to be masked by a separate word.
Data Handling Instructions 5-19 Operation When the rung containing this instruction is true, data at the source address passes through the mask to the destination address. See the figure below. MVM MASKED MOVE Source B3:0 Mask F0F0 Dest B3:2 B3:2 before move 1111111111111111 source B3:0 0101010101010101 Mask F0F0 1111000011110000 B3:2 after move 0101111101011111 Mask data by resetting bits in the mask; pass data by setting bits in the mask to one.
5-20 Data Handling Instructions This instruction performs a bit-by-bit logical AND. The operation is performed using the value at source A and the value at source B. The result is stored in the destination. And (AND) AND Bitwise AND Source A Source B Dest Table 5.
Data Handling Instructions 5-21 Or (OR) This instruction performs a bit-by-bit logical OR. The operation is performed using the value at source A and the value at source B. The result is stored in the destination. OR Bitwise Inclusive OR Source A B3:2 16C8h< Source B B3:3 EF0Ch< Dest B3:4 FFCCh< Fixed SLC SLC SLC SLC SLC 5/01 5/02 5/03 5/04 5/05 • • • • Output Instruction • • Table 5.
5-22 Data Handling Instructions This instruction performs a bit-by-bit logical XOR. The operation is performed using the value at source A and the value at source B. The result is stored in the destination. Exclusive Or (XOR) XOR Bitwise Exclusive OR Source A B3:2 16C8h< Source B B3:3 EF0Ch< Dest B3:5 F9C4h< Table 5.
Data Handling Instructions This instruction performs a bit-by-bit logical NOT. The operation is performed using the value at source A. The result (one’s complement of A) is stored in the destination. Not (NOT) NOT NOT Source B3:2 0001011011001000< Dest B3:6 1110100100110111< Table 5.15 Truth Table for A Not = Dest Fixed SLC SLC SLC SLC SLC 5/01 5/02 5/03 5/04 5/05 • • 5-23 • • • • A Dest 0 1 1 0 The source and destination must be word addresses.
5-24 Data Handling Instructions Use the NEG instruction to change the sign of the source and then place it in the destination. The destination contains the two’s complement of the source. For example, if the source is 5, the destination would be -5. Negate (NEG) The source and destination must be word addresses.
Data Handling Instructions FIFO and LIFO Instructions Overview 5-25 FIFO (First in First out) instructions load words into a file and unload them in the same order as they were loaded. The first word in is the first word out. LIFO (Last in First out) instructions load words into a file and unload them in the opposite order as they were loaded. The last word in is the first word out. Entering Parameters Enter the following parameters when programming these instructions.
5-26 Data Handling Instructions Effects on Index Register S:24 The value present in S:24 is overwritten with the position value when a false-to-true transition of the FFL/FFU or LFL/LFU rung occurs. For the FFL/LFL, the position value determined at instruction entry is placed in S:24. For the FFU/LFU, the position value determined at instruction exit is placed in S:24. When the DN bit is set, a false-to-true transition of the FFL/LFL rung does not change the position value or the index register value.
Data Handling Instructions 5-27 Table 5.
5-28 Data Handling Instructions LFL and LFU instructions are used in pairs. The LFL instruction loads words into a user-created file called a LIFO stack. The LFU instruction unloads words from the LIFO stack in the opposite order as they were entered. LIFO Load (LFL) and LIFO Unload (LFU) LFL LIFO Load Source N7:71 LIFO #N7:80 Control R6:1 Length 10< Position 0< Instruction parameters have been programmed in the LFL - LFU instruction pair shown below.
Data Handling Instructions 5-29 LFL Instruction Operation When rung conditions change from false-to-true, the LFL enable bit (EN) is set. This loads the contents of the source, N7:10, into the stack element indicated by the position number, 9. The position value then increments. The LFL instruction loads an element at each false-to-true transition of the rung, until the stack is filled (34 elements). The processor then sets the done bit (DN), inhibiting further loading.
5-30 Data Handling Instructions Notes: Publication 1747-RM001G-EN-P - November 2008
Chapter 6 Program Flow Instructions This chapter contains general information about the program flow instructions and explains how they function in your application program. Each of the instructions includes information on: • what the instruction symbol looks like. • how to use the instruction. Table 6.1 Program Flow Instructions Instruction Mnemonic Instruction Name Purpose Page JMP and LBL Jump to Label and Label Jump forward or backward to the specified label instruction.
6-2 Program Flow Instructions Jump to Label (JMP) and Label (LBL) Use these instructions in pairs to skip portions of the ladder program. (JMP) Table 6.2 Program Function ]LBL[ Fixed SLC SLC SLC SLC SLC 5/01 5/02 5/03 5/04 5/05 • • • • • • If the Rung Containing the Jump Instruction is Then the Program True Skips from the rung containing the JMP instruction to the rung containing the designated LBL instruction and continues executing. You can jump forward or backward.
Program Flow Instructions 6-3 Using LBL This input instruction is the target of JMP instructions having the same label number. You must program this instruction as the first instruction of a rung. This instruction has no control bits. You can program multiple jumps to the same label by assigning the same label number to multiple JMP instructions. However, label numbers must be unique.
6-4 Program Flow Instructions Nesting Subroutine Files Nesting subroutines allows you to direct program flow from the main program to a subroutine and then on to another subroutine. The following rules apply when nesting subroutines. • With Fixed and SLC 5/01 processors, you can nest subroutines up to four levels • With SLC 5/02 and higher processors, you can nest subroutines up to eight levels.
Program Flow Instructions 6-5 You must program each subroutine in its own program file by assigning a unique file number (3 to 255) IMPORTANT Fixed and SLC 5/01 specific - The JSR instruction cannot be programmed in nested output branches. A compiler error will occur if a rung containing multiple outputs with conditional logic and a JSR instruction is encountered. Using SBR The target subroutine is identified by the file number that you entered in the JSR instruction.
6-6 Program Flow Instructions Master Control Reset (MCR) (MCR) Table 6.3 Controller Function Fixed SLC SLC SLC SLC SLC 5/01 5/02 5/03 5/04 5/05 • • • Use MCR instructions in pairs to create program zones that turn off all the non-retentive outputs in the zone. Rungs within the MCR zone are still scanned, but scan time is reduced due to the false state of non-retentive outputs.
Program Flow Instructions ATTENTION 6-7 If you start instructions such as timers or counters in an MCR zone, instruction operation ceases when the zone is disabled. Re-program critical operations outside the zone if necessary. The TOF timer activates when placed inside of a false MCR zone. The MCR instruction is not a substitute for a hard-wired master control relay.
6-8 Program Flow Instructions When this instruction is executed, it causes the processor to enter the Suspend Idle mode and stores the Suspend ID in word 7 (S:7) of the status file. All outputs are de-energized. Suspend (SUS) Use this instruction to trap and identify specific conditions for program debugging and system troubleshooting.
Program Flow Instructions 6-9 Refer to Entering Mask Values on page 5-17 for information about entering mask. Length - For SLC 5/03 and higher processors, this parameter is used to transfer more than one word per slot. Valid value is from 1 to 32. This instruction allows you to update the outputs prior to the normal output scan. When the IOM instruction is enabled, the program scan is interrupted to transfer data to a specified I/O slot through a mask. The program scan then resumes.
6-10 Program Flow Instructions I/O Refresh (REF) Using an SLC 5/02 Processor (REF) SLC 5/02 Processor Fixed SLC SLC SLC SLC SLC 5/01 5/02 5/03 5/04 5/05 • • • • The REF instruction has no programming parameters. When it is evaluated as true, the program scan is interrupted to execute the I/O scan and service communication portions of the operating cycle (write outputs, service comms, read inputs). The scan then resumes at the instruction following the REF instruction.
Chapter 7 Application Specific Instructions This chapter contains general information about the application specific instructions and explains how they function in your application program. Each of the instructions includes information on: • what the instruction symbol looks like. • how to use the instruction. Table 7.
7-2 Application Specific Instructions These instructions simplify your ladder program by allowing you to use a single instruction or pair of instructions to perform common complex operations. About the Application Specific Instructions In this chapter you will find a general overview preceding groups of instructions. Before you learn about the instructions in each of these groups, we suggest that you read the overview that precedes each section. This chapter contains the following overviews.
Application Specific Instructions 7-3 Status bits of the control element may be addressed by mnemonic. They include: – Unload Bit UL (bit 10) stores the status of the bit exited from the array each time the instruction is enabled. – Error Bit ER (bit 11), when set, indicates the instruction detected an error such as entering a negative number for the length or position. Avoid using the output bit when this bit is set. – Done Bit DN (bit 13), when set, indicates the bit array has shifted one position.
7-4 Application Specific Instructions Effects on Index Register S:24 The shift operation clears the index register S:24 to zero. BSL and BSR are output instructions that load data into a bit array one bit at a time. The data is shifted through the array, then unloaded one bit at a time.
Application Specific Instructions 7-5 Use BSR When the rung goes from false-to-true, the enable bit (EN bit 15) is set and the data block is shifted to the right (to a lower bit number) one bit position. The specified bit at the bit address is shifted into the last bit position. The first bit is shifted out of the array and stored in the unload bit (UL bit 10) in the status byte of the control element. The shift is completed immediately.
7-6 Application Specific Instructions Applications Requiring More than 16 Bits When your application requires more than 16 bits, use parallel multiple sequencer instructions. TIP Sequencer Output (SQO) Sequencer Compare (SQC) If a String element address is used for the file parameter, the maximum length for SLC 5/03 and higher processors is 41 words. Additionally, String element boundaries cannot be crossed.
Application Specific Instructions 7-7 You can address the mask, source, or destination of a sequencer instruction as a word or file. If you address it as a file, the instruction automatically steps through the source, mask, or destination file. TIP • Control (SQO, SQC) is the control structure that stores the status byte of the instruction, the length of the sequencer file, and the instantaneous position in the file. You should not use the control address for any other instruction. Table 7.
7-8 Application Specific Instructions TIP If you alter a length value with your ladder program, make certain that the altered value is valid. • Position is the word location or step in the sequencer file from/to which the instruction moves data. A position value that points past the end of the programmed file causes a runtime major error to occur. TIP You may use the reset (RES) instruction to reset a sequencer. All control bits (except FD) will be reset to zero. The Position will also be set to zero.
Application Specific Instructions 7-9 The bits mask data when reset and pass data when set. The instruction will not change the value in the destination word unless you set mask bits. The mask can be fixed or variable. If you enter a hexadecimal code, it is fixed. If you enter an element address or a file address for changing the mask with each step, it is variable. The following figure indicates how the SQO instruction works. SQO SEQUENCER File Mask Dest Control Length Position Destination O:14.
7-10 Application Specific Instructions Use SQC When the status of all non-masked bits in the source word match those of the corresponding reference word, the instruction sets the found bit (FD) in the control word. Otherwise, the found bit (FD) is cleared. The bits mask data when reset and pass data when set. The instruction will not change the value in the destination word unless you set the mask bits. The mask can be fixed or variable. If you enter a hexadecimal code, it is fixed.
Application Specific Instructions 7-11 Applications of the SQC instruction include machine diagnostics. The following figure explains how the SQC instruction works. SQC SEQUENCER File Mask Source Control Length Position (EN) (DN) (FD) COMPARE #B10:11 FFF0 I:3.0 R6:21 4 2 Input Word I:3.
7-12 Application Specific Instructions The SQL instruction stores 16-bit data into a sequencer load file at each step of sequencer operation. The source of this data can be an I/O or storage word address, a file address, or a constant. Sequencer Load (SQL) Enter Parameters SQL Sequencer Load File #B20:0 Source I:1.0 Control R6:3 Length 2< Position 1< EN Enter the following parameters when programming this instruction.
Application Specific Instructions 7-13 • Control is a control file address. The status bits, length value, and position value are stored in this element. Do not use the control file address for any other instruction. The control element is shown below. Table 7.
7-14 Application Specific Instructions Operation Instruction parameters have been programmed in the SQL instruction shown below. Input word I:1.0 is the source. Data in this word is loaded into integer file #N7:30 by the sequencer load instruction. SQL SEQUENCER File Source Control Length Position LOAD #N7:30 I:1.
Application Specific Instructions Read High-speed Clock and Compute Time Difference Overview 7-15 TDF and RHC instructions are used together. The RHC is used to record the start and stop time of an event. The TDF is used to calculate the time difference between the recorded start and stop times from the RHC instruction. RHC Instruction Operation SLC 500 maintains a 20-bit integer free running clock. This 20-bit value increments every 10 μs.
7-16 Application Specific Instructions TIP Measurements were calculated with both communication channels active and no devices connected to the processor. Worst case accuracy is improved by shutting down an unused communication channel. TDF Instruction Operation When the TDF is evaluated with a true rung state, the instruction calculates the number of 10 µs ticks that have elapsed from the Start value to the Stop value and places the result into the Destination location.
Application Specific Instructions 7-17 The Read High-speed Clock Instruction (RHC) provides a high performance timestamp for performance diagnostics and performing calculations such as velocity. Read High-speed Clock Instruction (RHC) Enter Parameters RHC Read High Speed Clock Dest N7:0 Fixed SLC SLC SLC SLC SLC 5/01 5/02 5/03 5/04 5/05 • • Destination - The address to store the current value of the 10 µs free running clock. It can be an integer address (Nx:x) or Float address (Fx:x).
7-18 Application Specific Instructions File Bit Comparison (FBC) and Diagnostic Detect (DDT) FBC File Bit Comparison Source #B3:0 Reference #B3:10 Result #N7:0 Control R6:0 Length 48< Position 0< Control R6:1 Length 10< Position 0< DDT Diagnostic Detect Source #B3:0 Reference #B3:10 Result #N7:0 Control R6:0 Length 48< Position 0< Control R6:1 Length 10< Position 0< EN Table 7.
Application Specific Instructions 7-19 After the instruction compares the last bit in two files, the done bit (bit 13 DN on the compare control element) is set. Then, when the rung goes false, the instruction resets the: • • • • enable bit. found bit (if set). compare done bit. result done bit (if set). The control position counters are reset on the next false-to-true rung transition.
7-20 Application Specific Instructions Enter Parameters To program these instructions, you need to provide the processor with the following information. • Source - The indexed address of your input file. • Reference - The indexed address of the file that contains the data with which you compare your input file. • Result - The indexed address of the file where the instruction stores the position (bit) number of each detected mismatch.
Application Specific Instructions 7-21 Use Status Bits To use the FBC or DDT instruction correctly, examine the control bits in both the comparison and result control elements. You address these bits by mnemonic. Table 7.8 FBC and DDT Status Bits Bit Function Comparison Control Bits Result Control Bits Enable EN (bit 15) Starts operation on a false-to-true rung transition.
7-22 Application Specific Instructions Source File #B3:0 15 08 07 bit 3 00 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 bit 31 Result File (2) (mismatched bit #s) #N7:0 Reference File (1) #B3:10 15 08 07 00 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 bit 40 bit 32 0 3 1 31 2 32 3 40 9 The FBC and DDT instructions detect mismatches and record their locations by bit number in a r
Application Specific Instructions Read Program Checksum (RPC) Fixed SLC SLC SLC SLC SLC 5/01 5/02 5/03 5/04 5/05 • • • 7-23 The Read Program Checksum (RPC) instruction copies the checksum of the user ladder program from either the processor’s RAM memory or from the installed memory module into the designated destination integer file location. The program checksum is a 16-bit value that is calculated for the entire ladder logic image, excluding the data table values.
7-24 Application Specific Instructions Notes: Publication 1747-RM001G-EN-P - November 2008
Chapter 8 Block Transfer Instructions This chapter contains general information about block transfer instructions and explains how they function in your application program. Each of the block transfer instructions includes information on: • what the instruction symbol looks like. • how to use the instruction. Table 8.1 Block Transfer Instructions Instruction Mnemonic Instruction Name Purpose Page BTR Block Transfer Read A BTR is used to receive data from a remote device.
8-2 Block Transfer Instructions A BTR or BTW instruction writes information into its control structure address (a three-word integer Control Block) when the instruction is entered. The processor uses these values to execute the transfer. You must enter an M1 file address into BTR Instructions and an M0 file address into BTW Instructions. However, each instruction uses both the M0 and M1 file for that one hundred word buffer (1 through 32).
Block Transfer Instructions 8-3 • Control - The control block is an integer data file address that stores all the block transfer control and status information. The control block is three words in length. Note that these integer file addresses should not be used for any other instructions. You should provide the following information for the control structure. – Rack - The I/O rack number (0 to 3) of the I/O chassis in which you placed the target I/O module.
8-4 Block Transfer Instructions Figure 8.1 Successful Block Transfer Control Information Control Bits EN TO Status Information Status Bits EW ST ER DN 122 3 4 5 Successful Block Transfer Read/Write Figure 8.1 illustrates a successful BT operation. 1. The SLC control program copies new data to the data file (BTW only) and solves the BT rung true, which sets the enable (EN) bit. 2.
Block Transfer Instructions TIP IMPORTANT TIP 8-5 Except for the time-out bit, TO (bit 08), do not modify any controller status bits while the block transfer is in progress. The BTR/BTW instruction must be scanned (true or false) in order to update the control and status bits. In order to conserve scan time, place each block transfer instruction in its own subroutine and only call the subroutine while the block transfer instruction is enabled. Table 8.
8-6 Block Transfer Instructions In addition to the control and status bits, the control block contains two other parameters the processor uses to execute the block transfer instructions. Requested Word Count, Word 1 (RLEN) This is used to configure BTR/BTW length information (0 to 64). Length is the number of BTR/BTW words read from or written to the RIO device. If RLEN = 0 for a BTW instruction, 64 words are sent.
Block Transfer Instructions 8-7 Instruction Operation 1. The scanner processes the BTR/BTW when it detects that the SLC control program rung, which contains the BTR/BTW, goes true. If the RIO scanner detects any problem at this point (such as invalid block transfer control field, or unconfigured device), the control structure word 2 fills with the error code and the ER bit (bit 12) is set. If no problems occur, the EW bit (bit 10) and ST bit (bit 14) are set in the control block.
8-8 Block Transfer Instructions IMPORTANT To prevent configuration conflicts, it is highly recommended that each M-file buffer (My:e.x00) should be used by only one block transfer instruction. Programming Examples Table 8.5 Block Transfer Programming Examples Figure 8.2, "Directional" on page 8-8 Figure 8.3, "Directional Repeating" on page 8-9 Figure 8.4, "Directional Continuous" on page 8-9 Figure 8.5, "Bi-directional Continuous" on page 8-9 Figure 8.
Block Transfer Instructions 8-9 Figure 8.3 Directional Repeating Figure 8.4 Directional Continuous Figure 8.
8-10 Block Transfer Instructions Figure 8.6 Bi-directional Alternating Figure 8.
Block Transfer Instructions 8-11 Comparison to the PLC-5 BTR and BTW BTR/BTW in SLC processors are quite similar to the instructions in the PLC-5. However, some differences exist between them, as shown in the table below. Table 8.6 Block Transfer Comparison Parameter SLC PLC-5 Control Block 3-element integer (N) type 5-element integer (N) type or 1-element block transfer (BT) type. EN (Enable Bit) Follows BT rung state. Gets set when BT rung goes true.
8-12 Block Transfer Instructions Notes: Publication 1747-RM001G-EN-P - November 2008
Chapter 9 Proportional Integral Derivative Instruction This chapter describes the Proportional Integral Derivative (PID) instruction. This is an output instruction that controls physical properties such as temperature, pressure, liquid level, or flow rate using process loops.
9-2 Proportional Integral Derivative Instruction The PID equation controls the process by sending an output signal to the control valve. The greater the error between the setpoint and process variable input, the greater the output signal, and vice versa. An additional value (feed forward/bias) can be added to the control output as an offset. The result of PID calculation (control variable) drives the process variable you are controlling toward the set point.
Proportional Integral Derivative Instruction The PID Instruction 9-3 The figure below shows a PID instruction with typical addresses for these parameters entered. PID PID Control Process Control Control Block Variable Variable Block Length N10:0 N10:28 N10:29 23 Place the PID instruction on a rung without any conditional logic. If a PID instruction goes false, the integral term is cleared.
9-4 Proportional Integral Derivative Instruction • Process Variable PV is an element address that stores the process input value. This address can be the location of the analog input word where the value of the input A/D is stored. This value could also be an integer value if you choose to pre-scale your input value to the range 0 to 16383. • Control Variable CV is an element address that stores the output of the PID instruction. The output value ranges from 0 to 16383, with 16383 being the 100% on value.
Proportional Integral Derivative Instruction PID Control Block Layout 9-5 The control block length is fixed at 23 words and should be programmed as an integer file. PID instruction flags (word 0) and other parameters are listed in the following table. Table 9.
9-6 Proportional Integral Derivative Instruction Controller Gain (Kc) Table 9.3 Controller Gain Parameter Tuning Parameter Descriptions Address Data Format Range Type KC - Controller Gain Word 3 word (INT) control 0 to 32,767 User Program Access read/write Gain Kc (word 3) is the proportional gain, ranging from 0 to 3276.7 (when RG = 0), or 0 to 327.67 (when RG = 1).
Proportional Integral Derivative Instruction 9-7 Rate Term (Td) Table 9.5 Rate Term Parameter Tuning Parameter Address Descriptions TD - Rate Term - Td Word 5 Data Format Range Type word (INT) control 0 to 32,767 User Program Access read/write Rate Td (word 5) is the Derivative term. The adjustment range is 0 to 327.67 minutes. Set this value to 1/8 of the integral gain Ti. TIP This word is not affected by the reset and gain range (RG) bit.
9-8 Proportional Integral Derivative Instruction When set for STI mode, the PID executes and updates the CV every time the PID instruction is scanned in the control program. When you select STI, program the PID instruction in the STI interrupt subroutine. The STI routine should have a time interval equal to the setting of the PID “loop update” parameter. Set the STI period in word S:30.
Proportional Integral Derivative Instruction 9-9 The deadband extends above and below the setpoint by the value entered. The deadband is entered at the zero crossing of the process variable and the setpoint. This means that the deadband is in effect only after the process variable enters the deadband and passes through the setpoint. The valid range is 0 to the scaled maximum, or 0 to 16,383 when no scaling exists. Scaled Error Table 9.
9-10 Proportional Integral Derivative Instruction Control (CM) Table 9.11 Control Mode Parameter Tuning Parameter Descriptions CM - Control Mode Address Data Format Range Word 0, Bit 2 binary (bit) 0 or 1 Type control User Program Access read/write Control mode, or forward-/reverse-acting, toggles the values E=SP-PV and E=PV-SP. When set (1) - Forward acting (E=PV-SP) causes the control variable to increase when the process variable is greater than the setpoint.
Proportional Integral Derivative Instruction 9-11 Example with the RG bit set: The reset term (TI) of 1 indicates that the integral value of 0.01 minutes/repeat (0.6 seconds/repeat) is applied to the PID integral algorithm. The gain value (KC) of 1 indicates that the error is multiplied by 0.01 and applied to the PID algorithm. Example with the RG bit clear: The reset term (TI) of 1 indicates that the integral value of 0.1 minutes/repeat (6.0 seconds/repeat) is applied to the PID integral algorithm.
9-12 Proportional Integral Derivative Instruction Derivative Rate Action Bit (DA) Table 9.16 Derivative Rate Action Bit Parameter Tuning Parameter Descriptions Address DA - Derivative Action Bit Word 0, Bit 7 Data Format Range Type binary (bit) control 0 or 1 User Program Access read/write When set (1), the derivative (rate) action (DA) bit causes the derivative (rate) calculation to be evaluated on the error instead of the process variable (PV).
Proportional Integral Derivative Instruction 9-13 Setpoint Out Of Range (SP) Table 9.19 Setpoint Out Of Range Parameter Tuning Parameter Descriptions Address Data Format Range Type SP - Setpoint Out of Range Word 0, Bit binary (bit) 11 0 or 1 status User Program Access read/write This bit is set (1) when the setpoint: • exceeds the maximum scaled value, or • is less than the minimum scaled value. PV Out Of Range (PV) Table 9.
9-14 Proportional Integral Derivative Instruction PID Rational Approximation Bit (RA) Table 9.22 PID Rational Approximation Parameter Tuning Parameter Address Descriptions RA - Rational Word 0, Approximation Bit 14 Data Format Range Type binary (bit) control 0 or 1 User Program Access read/write When the RA bit is set, rational approximation method is used for PID computation, resulting in a more accurate output. PID Enable (EN) Table 9.
Proportional Integral Derivative Instruction Input Parameters 9-15 The table below shows the input parameter addresses, data formats, and types of user program access. See the indicated pages for descriptions of each parameter. Table 9.
9-16 Proportional Integral Derivative Instruction Scaled Process Variable (SPV) Table 9.27 Scaled Process Variable Parameter Input Parameter Descriptions Address Data Format Range Type User Program Access SPV - Scaled Process Variable Word 14 word (INT) 0 to 16383 control read/write The SPV (Scaled Process Variable) is the analog input variable. If scaling is enabled, the range is the minimum scaled value (SMIN) to maximum scaled value (SMAX).
Proportional Integral Derivative Instruction 9-17 Setpoint Minimum Scaled (SMIN) Table 9.29 Setpoint Minimum Scaled Parameter Input Parameter Descriptions Address Data Range Format Type User Program Access SMIN Minimum Scaled Word 8 word (INT) control read/write (1) -32,768 to +32,766(1) SLC 5/02 valid range is -16383 to +16382.
9-18 Proportional Integral Derivative Instruction The table below shows the output parameter addresses, data formats, and types of user program access. See the indicated pages for descriptions of each parameter. Output Parameters Table 9.
Proportional Integral Derivative Instruction 9-19 Control Variable Percent (CV%) Table 9.32 Control Variable Percent Parameter Output Parameter Address Descriptions Data Format Range Type User Program Access CV% - Control Variable Percent word (INT) 0 to 100 status read only Word 16 CV% (Control Variable Percent) displays the control variable as a percentage. The range is 0 to 100%.
9-20 Proportional Integral Derivative Instruction Output Maximum (CVH) Table 9.34 Output Maximum Parameter Output Parameter Address Descriptions Data Format Range Type User Program Access CVH - Output Maximum word (INT) 0 to 100% control read/write Word 11 When the output limiting bit (OL) word 0, bit 3 of PID Control Block is enabled (1), the CVH (Control Value High) you enter is the maximum output (in percent) that the control variable attains.
Proportional Integral Derivative Instruction 9-21 Error code 0036 appears in the status file when a PID instruction runtime error occurs. Code 0036 covers the following PID error conditions, each of which has been assigned a unique single byte code value that appears in the MS byte of the second word of the control block. Runtime Errors Table 9.
9-22 Proportional Integral Derivative Instruction Table 9.36 PID Instruction Runtime Errors Error Code Description of Error Condition or Conditions Corrective Action 41H Scaling Selected Scaling Selected Scaling Deselected 1. Deadband < 0, or 1. Deadband < 0, or Change deadband to 0 < deadband < (Smax - Smin) < 16383 2. Deadband > (Smax - Smin), or 2. Deadband > 16383 Scaling Deselected Change deadband to 0 < deadband < 16383 3. Deadband > 16383 (5/02 specific) 51H 1.
Proportional Integral Derivative Instruction PID and Analog I/O Scaling 9-23 For the SLC 500 PID instruction, the numerical scale for both the process variable (PV) and the control variable (CV) is 0 to 16383. To use engineering units, such as PSI or degrees, you must first scale your analog I/O ranges within the above numerical scale. To do this, use the Scale (SCL) instruction and follow the steps below. 1.
9-24 Proportional Integral Derivative Instruction Using the SCL Instruction Use the following values in an SCL instruction to scale common analog input ranges to PID process variables Table 9.37 SLC Instruction Parameter 4 to 20mA 0 to 5V 0 to 10V Rate/10,000 12,499 10,000 5,000 Offset -4096 0 0 Use the following values in an SCL instruction to scale control variables to common analog outputs. Table 9.
Proportional Integral Derivative Instruction 9-25 Use the following values in an SCP instruction to scale control variables to common analog outputs. Table 9.40 SCP Instruction Parameter 4 to 20mA 0 to 5V 0 to 10V Input minimum 0 0 0 Input maximum 16383 16383 16383 Scaled minimum 6242 0 0 Scaled maximum 31208 16384 32764 Example The following ladder diagram shows a typical PID loop that is programmed in the STI mode.
9-26 Proportional Integral Derivative Instruction This rung immediately updates the analog input used for PV. IIM Rung 3:0 IMMEDIATE Slot Mask IN w MASK I:1.0 FFFF These two rungs ensure the analog input value to be scaled remains within the limits of 3277 to 16384. This is necessary to prevent “out of range” conversion errors in both the SCL and PID instructions. The latch bits can be used elsewhere in your program to identify the particular out of range condition that occurred.
Proportional Integral Derivative Instruction Application Notes 9-27 The following sections discuss: • • • • • • • input/output ranges. scaling to engineering units. output alarms. output limiting with anti-reset windup. the manual mode. PID rung state. time proportioning outputs. Input/Output Ranges The input module measuring the process variable (PV) must have a full scale binary range of 0 to 16383.
9-28 Proportional Integral Derivative Instruction For example, if measuring a full scale temperature range of -270°C (PV=0) to +1000°C (PV=16383), enter a value of -270 for Smin and 1000 for Smax. Remember that inputs to the PID instruction must be 0 to 16383. Signal conversions could be as follows: Table 9.
Proportional Integral Derivative Instruction 9-29 Output Limiting with Anti-Reset Windup You may set an output limit (percent of output) on the control output. When the instruction detects that the output (CO) has exceeded a limit, it sets an alarm bit (bit 10 for lower limit, bit 9 for upper limit) in word 0 of the PID control block, and prevents the output (CO) from exceeding either limit value. The instruction limits the output (CO) to 0 and 100% if you choose not to limit.
9-30 Proportional Integral Derivative Instruction PID Rungstate If the PID rung is false, the integral sum (words 17 and 18) is cleared and CV remains in its last state. I:2.0 ] [ 2 N7:10 (L) 1 I:2.0 ] [ 1 N7:10 (U) 1 N7:10 ] [ 1 I:2.0 ] [ 0 FRD B3 [OSR] 0 FROM BCD Source I1:1.
Proportional Integral Derivative Instruction 9-31 In this program, cycle time is the preset of timer T4:0. Cycle time relates to % on-time as follows: T4:0.PRE is the cycle time % on-time 100% output on-time Example - Time proportioning outputs PID PID Control Process Control Control Block Variable Variable Block Length N7:2 N7:0 N7:1 23 TON TIMER ON DELAY Timer Time Base Preset Accum (EN) T4:0 0.01 1000 0 (DN) Cycle Time of Output GRT O:1.0 (U) 0 GREATER THAN Source A T4:0.
9-32 Proportional Integral Derivative Instruction Notes: Publication 1747-RM001G-EN-P - November 2008
Chapter 10 ASCII Instructions This chapter contains general information about the ASCII instructions and explains how they function in your application program. Each of the instructions includes information on: • what the instruction symbol looks like. • how to use the instruction. Table 10.
10-2 ASCII Instructions ASCII Instruction Overview ASCII instructions are available in SLC 5/03 OS301 and above processors, and all SLC 5/04 and SLC 5/05 processors. There are two types of ASCII instructions. • ASCII port control - these include instructions that use or alter the communication channel for receiving or transmitting data. When using these instructions, the system configuration for channel 0 must be set to “User Mode.
ASCII Instructions 10-3 Table 10.2 ASCII Protocol Parameters Description Specification Data Bits Toggles between 7 and 8. The default is 8. Termination Characters Allows you to configure up to 2 ASCII characters. The default is CR. Append Characters Allows you to configure up to 2 ASCII characters. The AWA instruction adds the characters to the end of every string to serve as termination characters for the receiving device. The default is CR LF.
10-4 ASCII Instructions You configure append or end-of-line characters via the Channel Configuration screen. The default append characters are carriage return and line feed; the default end-of-line (termination) character is a carriage return. TIP All instructions except ACL and AHL will error if the port is disabled. Assign string addresses as follows. Table 10.4 Addressing Formats Format STf:e.s/b Examples Publication 1747-RM001G-EN-P - November 2008 Explanation ST String file f File number.
ASCII Instructions 10-5 Entering Parameters The control element for ASCII instructions includes eight status bits, an error code byte, and two character words. Table 10.
10-6 ASCII Instructions Test ASCII Buffer for Line (ABL) Use the ABL instruction to determine the total number of characters in the input buffer, up to and including the end-of-line characters (termination). This instruction looks for two termination characters that you configure via the ASCII port configuration screen. On a false-to-true transition, the processor reports the number of characters in the POS field of the ASCII control block. The serial port must be configured for User mode.
ASCII Instructions 10-7 The Error bit (ER) is set during the execution of the instruction if: • the instruction is aborted - serial port not in User mode. • the instruction is aborted due to channel mode change. • the Unload bit (UL) is set and the instruction is not executed. Number of ASCII Characters In Buffer (ACB) Use the ACB instruction to determine the total characters in the buffer.
10-8 ASCII Instructions The Error bit (ER) is set during the execution of the instruction if: • the instruction is aborted - serial port not in User mode. • the instruction is aborted due to channel mode change. • the Unload bit (UL) is set and the instruction is not executed. Use the ACI instruction to convert a numeric ASCII string to an integer value between -32,768 and 32,767.
ASCII Instructions ASCII Clear Receive and/or Transmit Buffer (ACL) ACL Ascii Clear Buffers Channel Receive Buffer Transmit Buffer 0 Yes No Fixed SLC SLC SLC SLC SLC 5/01 5/02 5/03 5/04 5/05 • Output Instruction • • 10-9 Use this instruction to clear an ASCII buffer. ASCII instructions are removed from the queue and then the Error bit (ER) is set. This instruction clears the ASCII buffers immediately upon the rung transitioning to a true state.
10-10 ASCII Instructions IMPORTANT For SLC 5/03 with OS302, Series C, FRN 7 and higher, when the ACL instruction is executed with: • the receive buffer set to No and the Transmit buffer set to Yes while channel 0 is in System Mode and configured for DF1. • the DF1 Remote/Local Passthru bit is set for Local (S34/6=1). Two actions occur.
ASCII Instructions String Concatenate (ACN) 10-11 The ACN instruction combines two strings using ASCII strings as operands. The second string is appended to the first and the result stored in the destination. Entering Parameters Enter the following parameters when programming this instruction. Fixed SLC SLC SLC SLC SLC 5/01 5/02 5/03 5/04 5/05 • • • Source A is the first string in the concatenation procedure. • Source B is the second string in the concatenation procedure.
10-12 ASCII Instructions Use the AEX instruction to create a new string by taking a portion of an existing string and linking it to a new string. String Extract (AEX) Entering Parameters AEX String Extract Source ST28:0 Index 32 Number 10 Dest ST14:3 Enter the following parameters when programming this instruction. Fixed SLC SLC SLC SLC SLC 5/01 5/02 5/03 5/04 5/05 • • • Output Instruction • Source is the existing string. The source value is not affected by this instruction.
ASCII Instructions 10-13 ASCII Handshake Lines (AHL) AHL Ascii Handshake Lines Channel 0 AND Mask 0FF03h OR Mask 0FDEBh Control R6:4 Channel Status 0000h Error 0 Use the AHL instruction to set or reset the RS-232 Data Terminal Ready (DTR) and Request to Send (RTS) handshake control lines for your modem. On a false-to-true transition, the processor uses the two masks to determine whether to set or reset the DTR and RTS lines, or leave them unchanged.
10-14 ASCII Instructions Example The following shows the channel status as 001F. Table 10.7 Control Block Structure Channel Status Bit 15 14 Bit Reserved Line 0 Channel Status 0 13 0 12 0 0 11 0 10 0 0 9 0 8 0 7 0 1 6 0 5 0 4 3 2 1 0 DTR DCD DSR RTS CTS 1 1 1 1 1 F Example The Error bit (ER) is set during the execution of the instruction if: • the instruction is aborted due to channel mode change.
ASCII Instructions 10-15 Use the ARD instruction to read characters from the buffer and store them in a string. To repeat the operation, the rung must go from false-to-true. ASCII Read Characters (ARD) Entering Parameters ARD ASCII Read Channel Dest Control String Length Characters Read Error EN 0 ST10:7 R6:5 20< 0 0 Enter the following parameters when programming this instruction.
10-16 ASCII Instructions The Error bit (ER) is set during the execution of the instruction if: • the instruction is aborted - serial port is not in User mode. • the modem is disconnected (control line selection is other than NO HANDSHAKING). • the instruction is aborted due to channel mode change. • the Unload bit (UL) is set. The instruction stops executing, but received characters are sent to the destination.
ASCII Instructions 10-17 Use the ARL instruction to read characters from the buffer, up to and including the end-of-line (termination) characters, and store them in a string. The end-of-line characters are specified via the ASCII Configuration screen. ASCII Read Line (ARL) Entering Parameters ARL ASCII Read Line Channel Dest Control String Length Characters Read Error EN 0 ST10:8 R6:6 16< 0 0 Enter the following parameters when programming this instruction.
10-18 ASCII Instructions When the program scans the instruction and finds the Done bit (DN) set, the processor then sets the Synchronous bit (EM). The EM bit acts as a secondary done bit corresponding to the program scan. The Error bit (ER) is set during the execution of the instruction if: • the instruction is aborted - serial port is not in User mode. • the modem is disconnected (when control line selection is other than “NO HANDSHAKING”). • the instruction is aborted due to channel mode change.
ASCII Instructions 10-19 Example The following conditions cause the processor to set the ASCII Error bit (S:5/15). • Invalid string length or string length of zero • Index value outside of range • Index value greater than the length of the source string The destination is not changed in any of the above conditions. ASCII String Compare (ASR) Use the ASR instruction to compare two ASCII strings. The system looks for a match in length and upper/lower case characters.
10-20 ASCII Instructions ASCII Write with Append (AWA) Use the AWA instruction to write characters from a source string to an external device. This instruction adds the one or two appended characters that you configure on the ASCII Configuration screen. The default is a carriage return and line feed appended to the end of the string. When using this instruction you can also perform in-line indirection. See page 10-21 for more information.
ASCII Instructions 10-21 When the program scans the instruction and finds the Done bit (DN) set, the processor then sets the Synchronous Done bit (EM) to act as a secondary done bit corresponding to the program scan. The Error bit (ER) is set during execution of the instruction if: • the modem is disconnected (control line selection is other than NO HANDSHAKING). • port is in System Mode and is configured for DH-485 or DF1 Radio Modem. • the Unload bit (UL) is set.
10-22 ASCII Instructions Examples For the following examples: N7:0 = 250 N7:1 = -37 F8:0 = 2.015000 F8:1 = 0.873000 Valid in-line direction: Input: Flow rate is currently [N7:0] GPH and contains [F8:0] PPM contaminants. Output: Flow rate is currently 250 GPH and contains 2.015000 PPM contaminants. Input: Current position is [N7:1] at a speed of [F8:1] RPM. Output: Current position is -37 at a speed of 0.873000 RPM.
ASCII Instructions 10-23 • Characters Sent (POS) is the number of characters that the processor sent to the display area (0 to 82). Only after the entire string is sent is this field updated (no running total for each character is stored). This field is display only. This value can be greater than the string length if inserted values from in-line indirection are used. If the string length is greater than 82, the string written to the destination is truncated to 82 characters.
10-24 ASCII Instructions ASCII Instruction Error Codes The following error codes indicate why the Error bit (ER) is set in the control data file (R6). Table 10.8 ASCII Error Codes Error Code (HEX) Conditions Resulting in the Setting of the ER Bit Recommended Action 00 No error. The instruction completed successfully. None required. 02 Operation cannot be completed because the modem went offline. Check modem cabling to communication channel.
ASCII Instructions ASCII Conversion Table 10-25 The table below lists the decimal, hexadecimal, and ASCII conversions. Table 10.
10-26 ASCII Instructions Table 10.9 ASCII Conversion Table (Continued) ASCII Hex Decimal Enter as Displayed as ! 21 33 ! or \21 ! ““““ 22 34 “““ or \22” ““““ # 23 35 # or \23 # $ 24 36 $ or \24 $ % 25 37 % or \25 % & 26 38 & or \26 & ‘ 27 39 ‘ or \27 ‘ ( 28 40 ( or \28 ( ) 29 41 ) or \29 ) * 2A 42 * or \2A or \2a * + 2B 43 + or \2B or \2b + , 2C 44 , or \2C or \2c , - 2D 45 - or \2D or \2d - . 2E 46 . or \2E or \2e .
ASCII Instructions 10-27 Table 10.
10-28 ASCII Instructions Table 10.
Chapter 11 Understanding Interrupt Routines This chapter contains general information about interrupt routines and explains how they function in your logic program. Each interrupt routine includes: • • • • an overview. programming procedure. operational description. associated bit description. In addition, each interrupt routine contains an application example that shows the interrupt routine in use. Table 11.
11-2 Understanding Interrupt Routines The user fault routine gives you the option of preventing a processor shutdown when a specific user fault occurs. The file is executed when any recoverable or non-recoverable user fault occurs. The file is not executed for non-user faults. User Fault Routine Overview Fixed SLC SLC SLC SLC SLC 5/01 5/02 5/03 5/04 5/05 • • • • A fault routine is programmed in a program file other than 2.
Understanding Interrupt Routines 11-3 Status File Data Saved Data in the following words is saved on entry to the user fault subroutine and re-written upon exiting the subroutine. • S:0 Arithmetic flags • S:13 and S:14 Math register • S:24 Index register Creating a User Fault Subroutine To use the user fault subroutine: 1. Create a subroutine file: valid range is 3-255. 2. Enter the file number in word S:29 of the status file.
11-4 Understanding Interrupt Routines User Interrupt Routine Application Example Suppose you have a program in which you want to control major errors 0020h (MINOR ERROR AT END OF SCAN) and 0034h (NEGATIVE VALUE IN TIMER PRE OR ACC) under the following conditions. • Prevent a processor shutdown if the overflow trap bit S:5/0 is set. Permit a processor shutdown when S:5/0 is set more than five times. • Prevent a processor shutdown if the accumulator value of timer T4:0 becomes negative.
Understanding Interrupt Routines 11-5 Fault Routine - Subroutine File 3 Word S:6 is the fault code (in decimal). EQU EQUAL Source A S:6 Fault Code 0020 0 (Enter &H20. Decimal Source B 32 equivalent 32 appears.) EQU EQUAL Source A S:6 0 Source B 52 Fault Code 0034 (Enter &H34. Decimal equivalent 52 appears.
11-6 Understanding Interrupt Routines Subroutine File 4 - Executed for Error 0020h S:5 ] [ 0 SBR SUBROUTINE CTU COUNT UP Counter Preset Accum EQU EQUAL Source A C5:0.ACC 0 Source B 5 C5:0 (U) S5:0 120 0 CU (CU) (DN) RET RETURN S:5 ] [ 0 S:5 (U) 0 S:1 (U) 13 RET RETURN END If the overflow trap bit, S:5/0 is set, counter C5:0 increments.
Understanding Interrupt Routines 11-7 Subroutine File 5 - Executed for Error 0034h The following rung toggles an output every time an error code of 0034h has occurred in the processor assuming the reason for the error was a negative value in timer T4:0. 0000 SBR Subroutine Major Error Halted S:1 U 13 LES Less Than (A
11-8 Understanding Interrupt Routines Selectable Timed Interrupt Overview This function allows you to interrupt the scan of the processor automatically, on a periodic basis, to scan a specified subroutine file. Afterward, the processor resumes executing from the point where it was interrupted. This section describes: Fixed SLC SLC SLC SLC SLC 5/01 5/02 5/03 5/04 5/05 • • • • • • • • STI programming procedure. STI operation and parameters. STD and STE instructions. STS instruction.
Understanding Interrupt Routines Operation 11-9 After you download your program and enter the REM Run mode, the STI begins operation as follows. 1. The STI timer begins timing. 2. When the STI interval expires, the STI timer is reset, the processor scan is interrupted and the STI subroutine file is scanned. 3. If while executing the STI subroutine, another STI interrupt occurs, the STI Pending bit (S:2/0) is set. 4. If while an STI is pending, the STI timer expires, the STI Lost bit (S:36/9) is set.
11-10 Understanding Interrupt Routines SLC 5/02 STI SLC 5/03 and Higher STI with Bit S:33/8 set SLC 5/03 and Higher STI with Bit S:33/9 cleared Input Scan Between slot updates Between word updates Between slot updates Program Scan Between instruction updates Between word updates Between rung updates Output Scan Between slot updates Between word updates Between slot updates Communications Between communication Between word packet packets updates Between communication packets Processor Ove
Understanding Interrupt Routines 11-11 Interrupt Priorities Table 11.3 Interrupt Priorities SLC 5/02 Processor SLC 5/03 and Higher Processors 1. User Fault Routine 1. User Fault Routine 2. Selectable Timed Interrupt Subroutine 2. Discrete Input Interrupt (DII) 3. Interrupt Subroutine (ISR) 3. Selectable Timed Interrupt Subroutine 4. Interrupt Subroutine (ISR) An executing interrupt can only be interrupted by an interrupt having higher priority.
11-12 Understanding Interrupt Routines STI Parameters The following parameters are associated with the STI function. These parameters have status file addresses that are described here. • STI file number (Word S:31) - This can be any number from 3 to 255. A value of zero disables the STI function. An invalid number generates fault 0023h. • Setpoint (Word S:30) - This is the time between the starting point of successive scans of the STI file. It can be any value from 10 to 2550 milliseconds.
Understanding Interrupt Routines 11-13 SLC 5/03 and higher processors: If this bit is set or reset by the user program or communications, it takes effect upon the STI timer expiration or next end of scan (whichever occurs first). • STI Executing Bit (S:2/2) - This bit is set when the STI file is being scanned and cleared when the scan is completed. The bit is also cleared on power-up and entry into the REM Run mode. • STI Resolution Selection Bit (S:2/10) - This bit is clear by default.
11-14 Understanding Interrupt Routines STI Example The following program will demonstrate a STI. The follwoing values need to be loaded into S:30 (1), S:31 (4) and S:2/10 (0) in STI setup. This will guarantee that subroutine (4) will be executed every 10 ms. The subroutine program will calculate the time difference from its last execution.
Understanding Interrupt Routines 11-15 The following rung will measure the time difference between consecutive interrupt subroutine executions. Integer N10.2 contains the number of microsecond "ticks" that have occured.
11-16 Understanding Interrupt Routines STD and STE Instructions The STD and STE instructions are used to create zones in which STI ladder execution cannot occur. The STI timer continues to operate at the rate present in word S:30. Selectable Timed Disable - STD Fixed SLC SLC SLC SLC SLC 5/01 5/02 5/03 5/04 5/05 • • • • When true, this instruction resets the STI enable bit and prevents the STI subroutine from executing.
Understanding Interrupt Routines 11-17 Program File 3 STI Example 3 The following program will demonstrate a STE and a STD. First Pass S:1 STE Selectable 0000 Timed Enable 15 Any Bit B3:0 Any Bit B3:2 0001 0 0 Any Bit B3:0 Any Bit B3:2 0002 1 0 STD Selectable 0003 STI interrupt execution does not occur between STD and STE.
11-18 Understanding Interrupt Routines Use the Discrete Input Interrupt (DII) for high-speed processing applications or any application that needs to respond to an event quickly. This instruction allows the processor to execute a ladder subroutine when the input bit pattern of a discrete I/O card matches a compare value that you programmed.
Understanding Interrupt Routines TIP 11-19 PLC users: The main difference between the DII and the PLC 5/40 PII is that the DII requires all stated transitions to occur prior to generating a count, while the PII requires that only one of the stated transitions occur. Also, the PLC term “count” is referred to as “preset” in the DII. Example The DII can be programmed to count items on a high-speed conveyer. Each time 100 items pass a photo-switch, the DII subroutine is executed.
11-20 Understanding Interrupt Routines Event Mode This mode is active when the preset value (S:50) contains a 0 or 1. 1. The DII reads the first byte of input data of a selected discrete input card at least once every 100µs.(1) Note that this “polling” of the input data has no effect on processor scan time. 2. When the input data matches the programmed masked value, the interrupt is generated. 3. The DII subroutine is executed.(2) 4. The cycle repeats.
Understanding Interrupt Routines 11-21 Interrupt Latency and Interrupt Occurrences Interrupt latency is the interval between DII detection and the start of the interrupt subroutine. DII interrupts can occur at any point in your program, but not necessarily at the same point on successive interrupts. Interrupts can occur between instructions in your program, inside the I/O scan (between slots), or between the servicing of communications packets.
11-22 Understanding Interrupt Routines Interrupt Priorities Interrupt priorities for the SLC 5/03 and higher processors are: 1. User fault routine. 2. Discrete Input Interrupt (DII). 3. STI Subroutine. 4. I/O Interrupt Subroutine. An executing interrupt subroutine can only be interrupted by the fault routine. TIP Under certain conditions, though, it is possible for a lower priority task to run during the DII execution.
Understanding Interrupt Routines 11-23 If you want to vary the number of items that are packaged together, simply change the number in the DII preset parameter using a MOV instruction. DII Parameters The following parameters are associated with the DII function. These parameters have status file addresses that are described here.
11-24 Understanding Interrupt Routines • Bit Mask (Word S:48) - You enter the bit-mapped value that corresponds to the bits you wish to monitor on the discrete I/O module (0 to 255). Only bits 0 to 7 are used in the DII function. Setting a bit indicates that you wish to include the bit in the comparison of the discrete I/O card’s bit pattern to the DII compare value (S:49). This value is applied on detection of the DII Reconfigure bit, each DII ISR exit, and at each end of scan (END, TND, or REF).
Understanding Interrupt Routines 11-25 For applications that measure the rate of incoming DII pulses while using a STI (Selectable Timed Interrupt), SLC 5/03 OS301 and above updates the DII accumulator prior to executing the first rung of the STI subroutine. Discrete Input Interrupt Application Example The following example shows how to use the Discrete Input Interrupt to control a high-speed application.
11-26 Understanding Interrupt Routines Ladder Diagram for the Bottling Application DII Example 4 The following program will demonstrate a DII. The following values need to be loaded into S:33/8 (1), S:46 (3), S:47 (1), S:49 (1) and S:50 (1) in the DII setup. This will guarantee that subroutine (3) will be executed every time that I:1.0/0 is true.
Understanding Interrupt Routines I/O Interrupt Overview (ISR) Fixed SLC SLC SLC SLC SLC 5/01 5/02 5/03 5/04 5/05 • • • • 11-27 This function allows a specialty I/O module to interrupt the normal processor operating cycle in order to scan a specified subroutine file. Interrupt operation for a specific module is described in the user’s manual for the module. Not all specialty I/O modules are capable of generating I/O interrupts.
11-28 Understanding Interrupt Routines Interrupt Subroutine (ISR) Content The Interrupt Subroutine (INT) instruction should be the first instruction in your ISR. This identifies the subroutine file as an I/O interrupt subroutine. The ISR contains the rungs of your application logic. You can program any instruction inside an ISR except a TND, REF, or SVC instruction. IIM or IOM instructions are needed in an ISR if your application requires immediate update of input or output points.
Understanding Interrupt Routines 11-29 Latency periods are: • SLC 5/02 interrupts are serviced within 2.4ms maximum. • SLC 5/03 and higher processors: If an interrupt occurs while the processor is performing a multi-word slot update and your interrupt subroutine accesses that same slot, the multi-word transfer finishes to completion prior to performing the interrupt subroutine slot access.
11-30 Understanding Interrupt Routines TIP SLC 5/02 specific: It is important to understand that the I/O pending bit associated with the interrupting slot remains clear during the time that the processor is waiting for the fault routine or STI subroutine to finish. SLC 5/03 and higher processors: The I/O pending bit is always set when the interrupt occurs. You can examine the state of these bits within your higher priority interrupt routines.
Understanding Interrupt Routines 11-31 • ISR Number - Specifies the subroutine file number that will be executed when an I/O interrupt is generated by an I/O module. The ISR Numbers are not part of the status file, but they are part of the I/O configuration for each slot in the SLC system. • I/O Slot Enables (Words S:11 and S:12) - These words are bit mapped to the 30 I/O slots. Bits S:11/1 through S:12/14 refer to slots 1 through 30. Bits S:11/0 and S:12/15 are reserved.
11-32 Understanding Interrupt Routines • I/O Interrupt Executing (Word S:32) - This word contains the slot number of the specialty I/O module that generated the currently executing ISR. This value is cleared upon completion of the ISR, run mode entry, or upon power up. You can interrogate this word inside of your DII or STI subroutine or fault routine if you wish to know if these higher priority interrupts have interrupted an executing ISR.
Understanding Interrupt Routines 11-33 IIE Operation When true, this instruction sets the I/O interrupt enable bits (S:27/1 through S:28/14) corresponding to the slots parameter of the instruction. Interrupt subroutines of the affected slots regain the ability to execute when an interrupt request is made. If an interrupt was pending (S:25/1 through S:26/14) and the pending slot corresponds to the IIE slots parameter, the ISR associated with that slot executes immediately.
11-34 Understanding Interrupt Routines This instruction resets the pending status of the specified slots and informs the corresponding I/O modules that you have aborted their interrupt requests. This instruction is not required to configure a basic I/O interrupt application.
Chapter 12 SLC Communication Instructions This chapter contains general information about the SLC communication instructions. Each of the instructions includes information on: • what the instruction symbol looks like. • how to use the instruction. Table 12.1 Communication Instructions 1 Instruction Mnemonic Instruction Name Purpose Page SVC Service Communications The SVC instruction interrupts the program scan to execute the service communication portion of the operating cycle.
12-2 SLC Communication Instructions About the Communication Instructions Use the SVC instruction to enhance communication performance of your processor. Use the various message instructions to send and receive data from other processors and devices. In this chapter you will find a general overview preceding each type of instruction. • Service Communication instruction for SLC 5/02 and higher processors. • General message instruction for the SLC 5/02 and higher processors.
SLC Communication Instructions Service Communications (SVC) SVC SERVICE Channel Channel SLC 5/03 and higher Fixed SLC SLC SLC SLC SLC 5/01 5/02 5/03 5/04 5/05 • Use an SLC 5/02 Processor The SVC instruction is an output instruction that has no programming parameters. When it is evaluated as true, the program scan is interrupted to execute the service communications part of the operating cycle. The scan then resumes at the instruction following the SVC instruction.
12-4 SLC Communication Instructions The following status bits let you customize or monitor communications servicing. Table 12.
SLC Communication Instructions The message instruction is an output instruction that lets you read or write data from one processor to another processor via the communication channel(s). The SLC 5/02 processor can service one message instruction at any given time. The SLC 5/03 and higher processors can service up to four message instructions per channel at a time, for a maximum of eight message instructions at any given time.
12-6 SLC Communication Instructions Figure 12.1 SLC 5/02 Messaging Example with MSG Timeout MSG_TRIGGER B3:0 0000 0 MSG_ST_BIT N9:0 0001 14 SLC_502_MSG MSG Read/Write Message Read/Write Target Device Control Block Control Block Length Setup Screen MSG_TIMEOUT TON Timer On Delay Timer Time Base Preset Accum MSG_TIMEOUT/DN T4:0 DN MSG_DN_BIT N9:0 0002 13 MSG_ER_BIT N9:0 12 0003 Publication 1747-RM001G-EN-P - November 2008 EN Read 500CPU N9:0 7 EN T4:0 1.
SLC Communication Instructions 12-7 Figure 12.2 SLC 5/02 Repeating Messaging Example with MSG Timeout SLC_502_MSG MSG Read/Write Message Read/Write Target Device Control Block Control Block Length Setup Screen 0000 MSG_ST_BIT N9:0 0001 14 MSG_TIMEOUT TON Timer On Delay Timer Time Base Preset Accum MSG_TIMEOUT/DN T4:0 DN 0002 13 12 0003 DN ER EN T4:0 1.
12-8 SLC Communication Instructions TIP If you consistently enable more MSG instructions than the buffers and queues can accommodate, the order in which MSG instructions enter the queue is determined by the order in which they are scanned. This means MSG instructions closest to the beginning of the program enter the queue regularly and MSG instructions later in the program may not ever enter the queue.
SLC Communication Instructions 12-9 Figure 12.4 SLC 5/03, SLC 5/04, and SLC 5/05 Repeating Messaging Example SLC_503_504_505_MSG MSG Read/Write Message Type Read/Write Target Device Local/Remote Control Block Control Block Length Setup Screen 0000 MSG_DN_BIT N9:0 0001 13 EN Peer-To-Peer Read 500CPU Local N9:0 14 DN ER MSG_EN_BIT N9:0 U 15 MSG_ER_BIT N9:0 12 0002 END For the SLC 5/05 Channel 1 Ethernet, TCP/IP protocol is used to establish Ethernet connections, in order to send the MSG commands.
12-10 SLC Communication Instructions Table 12.
SLC Communication Instructions 12-11 MSG Instruction Configuration Options The following configuration options are available on all SLC 5/02 and higher processors. • Peer-to-peer Read/Write on a local network to another SLC 500 processor • Peer-to-peer Read/Write on a local network to a 485CIF device (PLC-2 emulation) In addition, the following configuration options are available on all SLC 5/03 and higher processors.
12-12 SLC Communication Instructions • Local or Remote identifies if the message is sent to a device on a local network, or to a remote device on another network through a bridge. Valid options are: – Local, if the target device is on the local network – Remote, if the target device is on a remote network(1) • Control Block is an integer file address that you select. It is a block of words, containing the status bits, target file address, and other data associated with the message instruction.
SLC Communication Instructions 12-13 MSG Instruction Setup Screen Parameters Parameters for This Controller • Data Table Address – For a Read, this is the starting address which receives the data that is read from the target device. – For a Write, this is the starting address of the data which is written to the target device. – For Modbus RTU Master, this is the starting address to receive or send data. • Size in Elements – Specifies the length of the message in elements.
12-14 SLC Communication Instructions Table 12.6 MSG Instruction Maximum Number of Elements for Modbus RTU Master File Types Channel 0 on SLC 5/03, SLC 5/04, SLC 5/05 B 1856 bits N 116 words F 58 registers (32-bit) • Channel(1) Specifies the communication channel that is used to transmit the message request.
SLC Communication Instructions 12-15 Message Timeout for any SLC 5/05 channel 1 MSG cannot be modified in the Ethernet Message Setup dialog box. It is assigned by the processor and is determined by adding the Channel 1 MSG Connection Timeout to the MSG Reply Timeout, then adding five seconds. This value can be modified by changing one or both of the timeout values in the channel 1 channel configuration screen. The modified message timeout applies to all MSG instructions.
12-16 SLC Communication Instructions Specifies the node number of the target device that is receiving the message. Table 12.7 Valid Range of Local Node Address, Local Bridge Address, and Remote Station Address Parameters Protocol Decimal Octal DH-485 0-31 0-37 DH+ 0-63 0-77 DF1 0-254 0-376 Processors running OS Series C, FRN 6 and higher, can execute a broadcast write MSG command by entering in a target device local node address of 255 (decimal) using RSLogix 500 version 5.20 or higher.
SLC Communication Instructions 12-17 • Local Bridge Addr (dec)/(oct)(1) (2) Specifies the node number of the bridge device on the local network. Refer to page 12-16 for the valid range of addresses. • Remote Bridge Addr (dec)(1) Specifies the node number of the bridge device on the bridging network, when the bridge is configured for gateway mode. Otherwise, leave at 0. • Remote Station Addr (dec)(1) Specifies the node number of the target device on the remote network.
12-18 SLC Communication Instructions • Data Table Address This variable defines the starting address in the local controller. Valid file types for the Data Table Address are shown below: Table 12.8 Valid File Types for Data Table Address Message Read Message Write Bit (B) Bit (B) Integer (N) Integer (N) Floating Point (F) Floating Point (F) Only Bit (B) and Integer (N) file types are valid for Modbus Command messages.
SLC Communication Instructions 12-19 Message Type File Type Element Size Maximum Number of Elements per Message Modbus Commands B, N (command 5) 1-bit 1 B, N, F (command 6) 1-word or 32-bit register (float file type) 1 B, N (commands 1, 2, and 15) 1-bit 1856 Modbus bit elements (116 words) Commands 1 and 2 are read-only, command 15 is write-only.
12-20 SLC Communication Instructions Here are two examples of Read Register commands.
SLC Communication Instructions 12-21 Example 4: A 32-bit Write Request for a Float (F) command RSLogix 500 Data View (dec) SLC Processor (hex) MLX Processor (hex) RSLogix 500 Data View (dec) Write no swap 123456 47F1 2000 Writ e wo rd-sw ap 47F1 2000 1.086583e-19 2000 47F1 123456 error Similar to the Read Register command, – If the source file is a Floating file (Example 3), word-swap is recommended. – If the source file is an Integer file (Example 4), word-swap is unnecessary.
12-22 SLC Communication Instructions If the message timeout is set to zero, the message instruction will never timeout. Set the Time Out bit (TO = 1) to flush a message instruction from its buffer if the destination device does not respond to the communications request. • Modbus - MB Data Address (1-65536) Modbus addressing is limited to 16 bits per memory group, each with a range of 1 to 65,536.
SLC Communication Instructions 12-23 The default Slave Node Address is 1. The range is 0 to 247. Zero is the Modbus broadcast address and is only valid for Modbus write commands (5, 6, 15 and 16). TIP To initiate a broadcast message on a Modbus network, set the slave node address to 0. Do not initiate more than one Modbus broadcast message at a time. When sequentially triggering multiple Modbus broadcast messages, insert at least 10 msec. delay in between each message.
12-24 SLC Communication Instructions Figure 12.2 “This Controller” Parameters Modbus Command Modbus command is configured at rung setup. If a Channel configured for Modbus Master is selected in the Channel field of the Message Setup Screen, the following Modbus Command options will become available. The controller supports eight Modbus commands.
SLC Communication Instructions 12-25 capable of exchanging data with the device.
12-26 SLC Communication Instructions Configure MultiHop Tab To message to an Ethernet Network Interface (ENI) or MicroLogix 1100, enter the target device’s IP address in the first row ‘To Address’ field.
SLC Communication Instructions 12-27 MSG Instruction Setup Screen Status Bits The column in the table below lists the various status bits associated with the SLC 500 MSG instruction as displayed in the RSLogix 500 MSG instruction setup screen. Table 12.
12-28 SLC Communication Instructions With an SLC 5/02 MSG instruction, the ladder logic must reset the Timeout Bit before triggering the MSG instruction. TIP When programming timeout control in SLC 5/03 and higher processors, omit the Timeout Bit manual reset rung. • No Response Bit NR (bit 9) is set if the target processor responds to the MSG instruction that it cannot process the message at the current time (for DH-485 and DH+ protocols only). This means that the MSG should be retried.
SLC Communication Instructions 12-29 • Start Bit ST (bit 14) is set when the processor receives acknowledgment (ACK) from the target device. The ST bit is reset when the DN, ER, or TO bit is set. Do not set or reset this bit. It is informational only. For SLC 5/05 Ethernet (channel 1) communications, the ST bit indicates internally that the Ethernet daughterboard has received a command and it is acceptable for a transmission attempt. The command has not yet been transmitted.
12-30 SLC Communication Instructions MSG Instruction Control Block Limitations for Manipulating the Control Block Bits Do not manipulate the MSG instruction control block values except as noted below. For example, do not clear the first word of the control block, do not unlatch the time-out control bit (except in an SLC 5/02 MSG instruction), and so on.
SLC Communication Instructions 12-31 Control Block Layouts The control block layout is shown below for 500CPU or PLC-5 controller as the target device. Table 12.
12-32 SLC Communication Instructions The control block layout is shown below for 485CIF as the target device. Table 12.
SLC Communication Instructions 12-33 Table 12.
12-34 SLC Communication Instructions Table 12.
SLC Communication Instructions 12-35 Table 12.
12-36 SLC Communication Instructions Table 12.
SLC Communication Instructions The following section describes the status bit sequencing for an SLC 5/03, SLC 5/04, or SLC 5/05 MSG instruction. Status Bit Sequencing for SLC 5/03, SLC 5/04, and SLC 5/05 MSG Instruction 1.Rung goes True. 1 EN 1 0 EW 1 0 ST 1 0 DN ER 12-37 2.Target node receives packet. 2 3.Acknowledge sent of successful receipt. 3 4.Not shown. 5.Target node processes packet successfully and returns data (read) or writes data (success).
12-38 SLC Communication Instructions Once the EN bit is set, it remains set until the entire MSG process is complete and either the DN, ER, or TO bit is set. The MSG Timeout period begins timing when the EN bit is set. If the timeout period expires before the MSG instruction completes it function, the ER bit is set and an error code (37H) is placed in the MSG block to inform you of the timeout error.
SLC Communication Instructions 12-39 Next End of Scan At the next end of scan or SVC, the SLC processor determines if it should examine the MSG queue for “something to do.” The processor bases its decision on the state of bits S:2/15, S:33/7, S:33/5, S:33/6, network communication requests from other nodes, and if previous MSG instructions are already in progress. If the SLC processor determines that it should not access the queue, the MSG instruction remains as it was.
12-40 SLC Communication Instructions Step 4 is not shown in the timing diagram. An ACK is Not Received If you do not receive an ACK, step 3 does not occur. Instead, either no response or a NAK (no acknowledge) is received. When this happens, the ST bit remains clear. These conditions can cause no response. • The target node is not there. • The target node does not respond because the packet became too corrupted in transmission to be properly received. • The response was corrupted in transmission back.
SLC Communication Instructions 12-41 For SLC 5/03 (OS301 and higher), SLC 5/04, and SLC 5/05 processors, there are four MSG buffers per channel. Each channel has its own 10-position MSG queue. The SLC processor unloads the two MSG queues into the MSG buffers evenly at end of scan or SVC. This gives both channels equal access to communications.
12-42 SLC Communication Instructions Table 12.17 MSG Instruction Error Codes (Continued) Error Code Description of Error Condition 19H Improperly formatted Logical ASCII Address string. String not properly terminated with a NULL character or the string length does not match the value in the length parameter. 20H Target Node responded with: Host has a problem and will not communicate. 30H Target Node responded with: Remote station host is not there, disconnected, or shutdown.
SLC Communication Instructions 12-43 Table 12.
12-44 SLC Communication Instructions Table 12.17 MSG Instruction Error Codes (Continued) Error Code Description of Error Condition FCH Target Node responded with: Disk file is write protected or otherwise inaccessible (off-line only). FDH Target Node responded with: Disk file is being used by another application; update not performed (off-line only). FFH Local communication channel is shut down.
SLC Communication Instructions 12-45 All three instructions use an integer control block for storing the instruction parameters and a configuration setup screen, similar to the MSG instruction. The CIP commands consist of a Service Code; the object Class, Instance, and Attribute; and Send and Receive Data (if required for the selected Service Code). The setup screen provides a list of standard CIP Services to select from, including: • • • • • • Read Assembly. Write Assembly. Read Parameter.
12-46 SLC Communication Instructions CEM Instruction Setup Screen Parameters The following sections provide parameters for the CEM instruction setup screens. Parameters for This Controller on the General Tab • 1747-SCNR Slot This drop-down field lists all of the local slots that contain ControlNet scanner (1747-SCNR) modules within the IO Configuration. Select the slot number of the particular scanner module that this explicit message will be initiated through.
SLC Communication Instructions 12-47 Parameters for Target Device on the General Tab • Message Timeout(x1 ms) The amount of time in milliseconds that the scanner will wait for a reply to the explicit message command. Range is 2 to 32767. • ControlNet Addr (dec) The target ControlNet node address. Valid range is 1 to 99. If you enter in the local scanner’s ControlNet node address, the command is executed by the local scanner.
12-48 SLC Communication Instructions • Class (hex)/(dec) Possible Classes are 0 to FF (hex). See Volume 1 of the CIP Common Specification for the list of defined Classes. You may either enter in a hexadecimal Class value in the (hex) field or a decimal Class value in the (dec) field. • Instance (hex)/(dec) Possible Instances are 0 to FFFF (hex). See Volume 1 of the CIP Common Specification for the list of valid Instances for each Class.
SLC Communication Instructions 12-49 • Error bit ER (word 0, bit 12) is set when the message has failed to complete successfully. This bit is reset the next time the message rung goes from false to true. Do not set or reset this bit. It is informational only. • Done bit DN (word 0, bit 13) is set when the message has completed successfully. This bit is reset the next time the message rung goes from false to true. Do not set or reset this bit. It is informational only.
12-50 SLC Communication Instructions A scanner code of 0x207 results in an error code of 1. All other scanner codes listed result in an Error Code of 2. Table 12.20 list all valid CEM instruction Error Codes. Table 12.20 Valid CEM Instruction Error Codes Error Code Description of Error Condition 0 No error. 1 Timeout error. ControlNet explicit message timed out by scanner. 2 Scanner error. See Scanner Status. 3 Configuration error. Send file length > 248 or invalid IOI size. 5 Processor error.
SLC Communication Instructions 12-51 Control Block Layout The control block layout is shown below. Table 12.
12-52 SLC Communication Instructions This is an output instruction that lets you initiate unconnected CIP Generic messages via a 1747-SDN DeviceNet scanner module installed in the local chassis. These messages can be initiated to any node on the same DeviceNet network as the 1747-SDN, as long as the node is in the scanner’s scan list. The scanner can be in either Idle mode or Run mode. Each scanner module can only process one DEM instruction at a time.
SLC Communication Instructions 12-53 Parameters for Target Device on the General Tab • Message Timeout(x1 sec) The amount of time in seconds that the processor will wait for a reply from the scanner to the explicit message command. Range is 0, 2 to 255. Like the Message Timeout in a standard MSG instruction, a value of 0 disables the Message Timeout and a value of 1 second gets bumped to 2 seconds upon instruction execution.
12-54 SLC Communication Instructions • Class (hex)/(dec) Possible Classes are 0 to FF (hex). See Volume 1 of the CIP Common Specification for the list of defined Classes. You may either enter in a hexadecimal Class value in the (hex) field or a decimal Class value in the (dec) field. • Instance (hex)/(dec) Possible Instances are 0 to FFFF (hex). See Volume 1 of the CIP Common Specification for the list of valid Instances for each Class.
SLC Communication Instructions 12-55 • Done bit DN (word 0, bit 13) is set when the message has completed successfully. This bit is reset the next time the message rung goes from false to true. Do not set or reset this bit. It is informational only. • Enabled bit EN (word 0, bit 15) is set after the message rung goes from false to true AND the scanner module accepts this message because it is not currently processing any other explicit messages.
12-56 SLC Communication Instructions All error codes listed above result in an error code of 2. Table 12.24 Complete List of Valid DEM Error Codes Error Code Description of Error Condition 0 No error. 1 Timeout error. DeviceNet explicit message timed out by processor. 2 Scanner error. See Scanner Status. 3 User error. DeviceNet explicit message aborted by user.
SLC Communication Instructions 12-57 Control Block Layout The control block layout is shown below. Table 12.
12-58 SLC Communication Instructions This output instruction lets you initiate connected CIP Generic messages via channel 1 on a SLC 5/05 processor. These messages can be initiated to EtherNet/IP nodes on the same Ethernet network as the SLC 5/05 or can be bridged through a ControlLogix gateway to nodes on remote ControlNet or Ethernet networks. The instruction is similar in operation to a standard MSG instruction.
SLC Communication Instructions 12-59 • Data Table Address (Send Data) If Size in Words (Send Data) is non-zero, then this field requires a starting integer (N) file address for storing the Send Data. • Data Table Address (Receive Data) If Size in Words (Receive Data) is non-zero, then this field requires a starting integer (N) file address for storing the Receive Data.
12-60 SLC Communication Instructions • Service Code (hex) This field is read-only unless the Custom Service is selected. Possible Service Codes are 1 to 7F (hex). See Volume 1 of the CIP Common Specification, Appendix A, for the list of valid explicit messaging Service Codes. • Class (hex)/(dec) Possible Classes are 0 to FFFF (hex). See Volume 1 of the CIP Common Specification for the list of defined Classes.
SLC Communication Instructions 12-61 Definitions for Message Status Bits on the General Tab The table below lists the various status bits associated with the EEM instruction as displayed in the EEM instruction setup screen. Table 12.
12-62 SLC Communication Instructions • Enabled bit EN (word 0, bit 15) is set after the message rung goes from false to true and there is space available in either the channel 1 message buffers or message queue. It remains set until message transmission is completed and the rung goes false. If the message rung conditions remain true, you may retrigger the message instruction by resetting this bit after either the ER or DN bit has been set, indicating that the previous execution has completed.
SLC Communication Instructions 12-63 Send Data Tab The Send Data Tab provides a convenient way of viewing and entering in data to be sent along with the explicit message command. The data is shown in byte format with a selectable radix of either Decimal or Hex/BCD. The display only shows the number of words that are defined in the Size in Words (Send Data) field, starting with the low byte of the first word as defined in the Data Table Address (Send Data) field.
12-64 SLC Communication Instructions Control Block Layout Table 12.
Chapter 13 SLC Communication Channels Use the information in this chapter to understand how to configure and monitor the SLC 500 communication channels including passthru. The following communication drivers are supported. Table 13.
13-2 SLC Communication Channels Communication Driver Overview DH-485 - The SLC 500 Fixed, SLC 5/01, SLC 5/02 and SLC 5/03 have a dedicated channel for DH-485. SLC 5/03, SLC 5/04 and SLC 5/05 RS-232 channel 0 can be reconfigured for DH-485. This network is a multi-master, token-passing network protocol capable of supporting up to 32 devices (nodes). This protocol allows: • monitoring of data and processor status, along with program uploading and downloading of any device on the network from one location.
SLC Communication Channels 13-3 DF1 Full-duplex - DF1 Full-duplex protocol (also referred to as DF1 point-to-point protocol) allows two devices to communicate with each other at the same time. This protocol allows: • transmission of information across full-duplex modems (dial-up, leased line, radio, or direct cable connections). • communication to occur between Allen-Bradley products and third-party products.
13-4 SLC Communication Channels DH-485 Communications The DH-485 network offers: • • • • • interconnection of 32 devices. multi-master capability. token passing access control. the ability to add or remove nodes without disrupting the network. maximum network length of 1219 m (4,000 ft). DH-485 Network Protocol The following section describes the protocol used to control message transfers on the DH-485 network. The protocol supports two classes of devices: initiators and responders.
SLC Communication Channels 13-5 DH-485 Network Initialization Network initialization begins when a period of inactivity exceeds the time of a link dead timeout. When the time for the link dead timeout is exceeded, usually the initiator with the lowest address claims the token. Building a network begins when the initiator that claimed the token tries to pass the token to the successor node.
13-6 SLC Communication Channels Setting Node Addresses The best network performance occurs when node addresses start at 0 and are assigned in sequential order. SLC 500 processors default to node address 1. The node address is stored in the processor status file (S:15L). Processors cannot be node 0. Also, initiators such as personal computers should be assigned the lowest numbered addresses to minimize the time required to initialize the network.
SLC Communication Channels 13-7 Configuring a Channel for DH-485 To configure an SLC processor channel for DH-485, do the following using your programming software: To bring up the Channel Configuration interface, double-click on the Channel Configuration icon. For an SLC 500 Fixed, SLC 5/01 and SLC 5/02 processor, enter in the Baud Rate and Node Address parameters. For SLC 5/03, SLC 5/04 and SLC 5/05 processors, define the location of the diagnostic file used for Channel Status here. See Table 13.
13-8 SLC Communication Channels 1. On the Channel 1 or 0 tab, choose DH-485 for your Driver. 2. Configure the communication driver characteristics according to Table 13.2. Table 13.2 Define these communication parameters when configuring an SLC 5/03 or higher processor for DH-485 communications. Tab Parameter Default Selections General Diagnostic File 0 Select an unused file (9 to 255) to store channel status information.
SLC Communication Channels 13-9 DH-485 Channel Status For SLC 5/03 (OS302, Series C and higher), SLC 5/04 (OS401, Series C and higher) and SLC 5/05, channel status data is stored in the diagnostic file defined on the Channel Configuration screen. Table 13.3 on page 13-9 explains information regarding the diagnostic counter data displayed. Double-click on the Channel Status Icon Located beneath the Configuration icon to bring up the Channel Status screen. See Table 13.
13-10 SLC Communication Channels Table 13.3 SLC 5/03 Channel 1 and SLC 5/03 and Higher Channel 0 DH-485 Channel Status (Continued) Status field Bytes Displays the Total Bad Packets Received 8 Number of incorrect data packets the processor has received. Packets with bad type byte 9 Number of messages that the processor could not receive because they were of an illegal type that contained a bad control byte.
SLC Communication Channels 13-11 The DH+network uses factory set time-outs to restart token-passing communication if the token is lost because of a defective or powered down node. Example The example below shows the connectivity of an SLC 5/04 processor to a PLC-5 processor using the DH+ protocol. A communication rate of 57.6K baud is used.
13-12 SLC Communication Channels Configuring Channel 1 for DH+ To configure an SLC 5/04 processor channel for DH+, do the following using your programming software. To bring up the Channel Configuration interface, double-click on the Channel Configuration icon. Define the location of the diagnostic file used for Channel Status here. See Table 13.5 on page 13-15 for diagnostic file details.
SLC Communication Channels 13-13 1. On the Channel 1 tab, choose DH+ for your Driver. 2. Configure the communication driver characteristics according to Table 13.4. Table 13.4 Define these communication parameters when configuring an SLC 5/04 for DH+ communications. Tab Parameter Default Selections General Diagnostic File 0 Select an unused file (9 to 255) to store channel status information. You must define a diagnostic file in order to be able to view channel 1 status. See Table 13.
13-14 SLC Communication Channels Double-click on the Channel Status Icon Located beneath the Configuration icon to bring up the Channel Status screen. See Table 13.5 for details concerning the DH+ Channel Status Screens for Messages, General, Data Sent with Acknowledgement, and Data Sent without Acknowledgement.
SLC Communication Channels 13-15 Table 13.5 SLC 5/04 Channel 1 DH+ Channel Status Status field Messages Word Displays the Received 0 Number of error-free messages the station has received. This number is the sum of the SDA and SDN received counters. Sent 1 Total number of messages sent by the station. This number is the sum of the send data acknowledge counters (SDA) and send data no acknowledge (SDN) transmit confirm counters.
13-16 SLC Communication Channels Table 13.5 SLC 5/04 Channel 1 DH+ Channel Status (Continued) Status field General Word Displays the Network dead 5 Number of times the station detects no traffic on the network. This usually occurs when the station with the token is powered down or is removed from the network. The other stations are waiting for the token to be passed to them. Eventually a network dead situation is declared and a claim token sequence is initiated. (See claims won for more information.
SLC Communication Channels 13-17 Table 13.5 SLC 5/04 Channel 1 DH+ Channel Status (Continued) Status field General Solicit rotations Received Data Sent with Received with error Acknowledgement (SDA) Word Displays the 30 Number of times a complete solicit successor of all stations not on the link is completed. A solicit successor occurs during a token pass around the link. Here a station that is currently not on the link is solicited to see if it has been added to the link.
13-18 SLC Communication Channels Table 13.5 SLC 5/04 Channel 1 DH+ Channel Status (Continued) Status field Word Displays the Transmit failed Data Sent with AcknowledTransmit NAK full gement (SDA) 25 Number of SDA messages sent by the station that were determined to be in error. This counter is the sum of the SDA transmit not ACKed and SDA transmit time-out counter. 26 Number of times the station received NAK to a message because the destination station was full.
SLC Communication Channels 13-19 This word is located in memory at S:99. If, S:34/3 is set, data in this memory location is transmitted every time the processor passes the DH+ token. Note that all other DH+ nodes see this data. • Global Status File. This file is located in memory at S:100 to S:163, representing one memory location for each of the 64 possible nodes on the DH+ network.
13-20 SLC Communication Channels • The word in the Global Status File corresponding to the SLC 5/04 processor’s DH+ address will be set to 0x0000 if any thing is done to inhibit the transmission of the Global Status Word from S:99.
SLC Communication Channels 13-21 Note that all 164 words are updated during each end-of-scan. The following table describes possible states of the DH+ node address and the value written to the Global Status Word (S:99). Table 13.
13-22 SLC Communication Channels Ethernet Communications This section: • • • • • describes SLC 5/05 performance considerations. describes Ethernet network connections and media. explains how the SLC 5/05 establishes node connections. lists Ethernet configuration parameters and procedures. describes configuration for subnet masks and gateways. The SLC 5/05 supports Ethernet communication via the Ethernet communication channel 1.
SLC Communication Channels 13-23 Optimal Performance: PC to SLC 5/05 Processor (2-node Ethernet network) Table 13.7 Optimal Performance: RSLinx to SLC 5/05 Processor (2-node Ethernet network) Operation Words MSG per Second Words per Second Single Typed Read 1 105 105 Single Typed Read 20 99 1980 Single Typed Read 100 86 8600 Single Typed Read 256 71 18176 SLC 5/05 and PC Connections to the Ethernet Network TCP/IP is the mechanism used to transport Ethernet messages.
13-24 SLC Communication Channels IMPORTANT The SLC 5/05 processor contains an RJ45 Ethernet connector which connects to standard Ethernet switches via 8-wire twisted pair straight-through cable. To access other Ethernet mediums, use RJ45 media converters or Ethernet switches that can be connected together via fiber, thin-wire, or thick-wire coaxial cables, or any other physical media commercially available with Ethernet switches. There are two ways to configure the SLC 5/05 Ethernet channel 1.
SLC Communication Channels 13-25 Define the location of the diagnostic file used for Channel Status here. See Table 13.10 on page 13-30 for diagnostic file details. Configure the communication driver characteristics according to Table 13.8.
13-26 SLC Communication Channels Table 13.8 Define these communication parameters when configuring an SLC 5/05 processor for Ethernet communications. Tab Parameter Default Selections General Diagnostic File 0 Select an unused file to store channel status information. You must define a diagnostic file in order to be able to view channel 1 status. The Diagnostic File Number must be an integer within the limits of 9 to 255. See Table 13.10 for a file description.
SLC Communication Channels 13-27 Table 13.8 Define these communication parameters when configuring an SLC 5/05 processor for Ethernet communications. (Continued) Tab Parameter Default Selections Inactivity Timeout(3) 30 minutes The amount of time (in minutes) that a MSG connection may remain inactive before it is terminated. The Inactivity Timeout has a 1 minute resolution and a range from 1 to 65,500 minutes. BOOTP Enable enabled The BOOTP enable switch.
13-28 SLC Communication Channels Table 13.
SLC Communication Channels 13-29 See Table 13.10 for details concerning the Ethernet Channel Status Screen.
13-30 SLC Communication Channels Table 13.10 SLC 5/05 Channel 1 Ethernet Channel Status Status field Commands Replies General Words Displays the number of Sent 0,1 Commands sent by the channel. Received 2,3 Commands received by the channel. Sent 4,5 Replies sent by the channel. Sent with error 6.7 Replies containing errors sent by the channel. Received 8,9 Replies received by the channel. Received with error 10,11 Replies containing errors received by the channel.
SLC Communication Channels 13-31 Table 13.10 SLC 5/05 Channel 1 Ethernet Channel Status (Continued) Status field Connections Port(1) Words Displays the number of Total Message Connections(2) 50 Total existing Ethernet message connections. Incoming Message Connections(2) 51 Existing incoming Ethernet message connections. Outgoing Message Connections(2) 52 Existing outgoing Ethernet message connections. Maximum Connections Allowed(3) 53 Maximum number of connections allowed.
13-32 SLC Communication Channels The host system’s BOOTP configuration file must be updated to service requests from SLC 5/05 processors. The following parameters must be configured. Table 13.11 BOOTP Configuration Parameters Parameter Description IP Address A unique IP Address for the SLC 5/05 processor. Subnet Mask Specifies the net and local subnet mask as per the standard on subnetting RFC 950, Internet Standard Subnetting Procedure.
SLC Communication Channels 13-33 Using the Rockwell BOOTP Utility The Rockwell BOOTP utility is a standalone program that incorporates the functionality of standard BOOTP software with a user-friendly graphical interface. It is located in the Utils directory on the RSLogix 5000 installation CD. It can also be downloaded from www.ab.com/networks/bootp/index.html web page. The device must have BOOTP enabled (factory default) to use the utility. To configure your device using the BOOTP utility: 1.
13-34 SLC Communication Channels Publication 1747-RM001G-EN-P - November 2008
SLC Communication Channels SLC 5/05 Embedded Web Server Capability 13-35 SLC 5/05 processors with OS501, Series C, FRN 6 (or higher) include an enhanced embedded web server (introduced in Series C, FRN 5) which allows viewing of not only module information, TCP/IP configuration, and diagnostic information, but also includes the data table memory map, data table monitor screen, and user-provided web pages via Ethernet using a standard web browser.
13-36 SLC Communication Channels Figure 13.2 SLC 5/05 Module Information Page TCP/IP Configuration This page displays a table with information about the current TCP/IP configuration parameters. Included are the module’s IP address, the subnet mask, gateway address, the Ethernet hardware address and whether BOOTP is enabled. Also included are the name server, secondary name server and the default domain name parameters, if configured. Figure 13.
SLC Communication Channels 13-37 Diagnostic Information This section gives you access to the various diagnostic information screens that are available. It is divided into two sections, the Network Stack Statistics and Application Level Statistics. The Network Stack Statistics detail information about the TCP/IP stack, while the Application Level Statistics are related to the Allen-Bradley Client Server Protocol (CSP) and Common Industrial Protocol (CIP) diagnostics.
13-38 SLC Communication Channels Data Table Memory Map The Data Table Memory Map page displays a list of the data table files, their type, and size in elements for a connected SLC 5/05, as shown in the following example. Figure 13.
SLC Communication Channels 13-39 Each file contains a hyperlink that takes you to the specific Data Table Monitor page for that file. When you click on a particular file, the Data Table Monitor page appears, displaying the contents of the data table file you selected. Figure 13.6 Data Table Monitor Page The available and default display formats depend on the data type of the file. Press the Prev or Next buttons to display the previous or next page of the data table file, if any.
13-40 SLC Communication Channels Data Table Monitor You may also go directly to the Data Table Monitor screen by selecting it on the home page or by clicking on D/T Monitor on the bottom row of the other pages. In this case, since a particular data file has not been chosen, a default screen is displayed. Figure 13.7 Default Data Table Monitor Screen From here you may enter in the starting data table address to display.
SLC Communication Channels 13-41 User Provided Pages You can use a text editor to generate up to 16 user-provided web pages. Each page is stored in four consecutive ASCII files of the SLC 5/05 processor. The channel configuration feature of RSLogix 500 (version 6.0 or later) allows you to select the starting file number and the number of user pages to be stored, as shown in the following example. Figure 13.8 Channel Configuration Screen in RSLogix 500 RSLogix 500 (version 6.
13-42 SLC Communication Channels HTML Pages Referencing Other Pages/Servers - following are some basic considerations when referencing other pages or servers. • Reference User Specified Pages in the SLC 5/05 by using the names user1.html through user16.html • To reference a page on the same processor, specify a URL such as /user2.html • To reference a page on another processor, specify a URL such as http://www.xxx.yyy.zzz/user2.html, where www.xxx.yyy.
SLC Communication Channels 13-43 When defining your custom tag, consider the following: Table 13.12 Custom Tags: Tag Item Description #elements If not specified, this defaults to one. If it is less than one, it also defaults to one. Each element is output using the same format (whether specified with %format or defaulted). %format Legal values are %d for decimal and %x for hexadecimal. The following file types allow the format to be specified.
13-44 SLC Communication Channels Generating Custom Data Table Monitor Pages You can generate Custom Data Table Monitor pages with your text editor then download them to the SLC 5/05 processor using RSLogix 500 version 6.0 or later. The first element of the file must contain a special tag as follows: where xx is the automatic refresh rate in seconds (01-99). A value outside the range defaults to a “snapshot” display. You can modify the refresh rate three different ways.
SLC Communication Channels Tag Item Description %format Legal values are %b for binary, %d for decimal, %0 for octal and %x for hexadecimal. The following file types allow the format to be specified. • Input • Output 13-45 • Status • Integer All other file types are displayed in an appropriate format. If a %format modifier is present, the format may be changed by clicking on the file type/number via a web browser. #expand Legal values are #c and #e.
13-46 SLC Communication Channels Figure 13.9 User Provided Pages Menu Click on the User Provided Page #X to display that specific page. Figure 13.10 User Provided Page #5 Displayed You can change the radix display of I, O, S, and N file addresses, which appear with an underline. 1. Go back to the User-Provided Custom Data Table Monitor page.
SLC Communication Channels 13-47 2. In the Address column, click on an underlined address to display the radix selection page. 3. Click on a radio button to select the desired radix type. To see the Sample Extended Format page: 1. Go back to the User-Provided Custom Data Table Monitor page. 2. In the Address column, click on the + before an address to display the Sample Extended Format. Click on the link under the file heading to display an ASCII dump of the ASCII file.
13-48 SLC Communication Channels Exporting User Provided Page Files from the SLC 5/05 Processor To export user provided pages to HTML files: 1. In the Project folder (under the Data Files folder), right click on the first block of four consecutive ASCII files you want to export. 2. Click on Properties. 3. Click on Export HTML. 4. Name the file and browse to the subdirectory to save it in. 5. Click OK. 6. Repeat this process for each desired user page file.
SLC Communication Channels DF1 Full-duplex Communications 13-49 DF1 Full-duplex protocol (also referred to as DF1 point-to-point protocol) is provided for applications where RS-232 point-to-point communication is required. This type of protocol supports simultaneous transmissions between two devices in both directions. You can use channel 0 as a programming port, or as a peer-to-peer port using the MSG instruction. In full-duplex mode, the SLC 5/03 (or higher) processor can send and receive messages.
13-50 SLC Communication Channels Define the location of the diagnostic file used for Channel Status here. For channel status details, refer to 13-53. 1. On the Channel 0 tab, choose DF1 Full-Duplex for your Driver. 2. Configure the communication driver characteristics according to table 13.15.
SLC Communication Channels 13-51 Table 13.15 Define these communication parameters when configuring a SLC 5/03, 5/04, or 5/05 processor for DF1 full-duplex communication. Tab Parameter Default Selections General Diagnostic File 0 SLC 5/03 (OS 302, Series C or higher), SLC 5/04 (OS 401, Series C or higher) and SLC 5/05 only. Select an unused file (9 to 255) to store channel status information. You must define a diagnostic file in order to be able to view channel 0 status. See Table 13.
13-52 SLC Communication Channels Table 13.15 Define these communication parameters when configuring a SLC 5/03, 5/04, or 5/05 processor for DF1 full-duplex communication. (Continued) Tab Parameter Default Selections Channel 0 System Error Detection CRC With this selection, you choose the how the processor checks the accuracy of each DF1 packet transmission. BCC: This algorithm provides a medium level of data security. It cannot detect: • transposition of bytes during transmission of a packet.
SLC Communication Channels 13-53 DF1 Full-duplex Channel Status Channel Status data is stored in the diagnostic file defined on the Channel 0 Configuration screen. See Table 13.25 for information regarding the diagnostic counter data displayed. Double-click on the Channel Status Icon Located beneath the Configuration icon to bring up the Channel Status screen. See the following table for details concerning the DF1 Full-duplex Channel Status Screen.
13-54 SLC Communication Channels Table 13.
SLC Communication Channels DF1 Half-duplex Communications 13-55 DF1 Half-duplex Master/Slave protocol provides a multi-drop single master/multiple slave network. In contrast to DF1 full-duplex, communication takes place in one direction at a time. The master device initiates all communication by “polling” each slave device. The slave device may only transmit data packets when it is polled by the master.
13-56 SLC Communication Channels master received the packet without error. When the DF1 half-duplex master re-broadcasts the broadcast write command, the initiating DF1 half-duplex slave receives and executes the command along with all of the other slave nodes receiving the broadcast packet. No acknowledgement or reply is returned.
SLC Communication Channels 13-57 Define the location of the diagnostic file used for Channel Status here. For Channel Status details, see page 13-68. 1. On the Channel 0 tab, choose DF1 Half-Duplex for your Driver. 2. Choose a Standard Polling Mode. 3. Configure the rest of the communication driver characteristics according to Table 13.16.
13-58 SLC Communication Channels Table 13.17 Define these parameters when configuring a SLC 5/03, 5/04, or 5/05 processor as a master station using standard polling mode to communicate with slave stations Tab Parameter Default Selections General Diagnostic File 0 SLC 5/03 (OS 302, Series C or higher), SLC 5/04 (OS 401, Series C or higher) and SLC 5/05 only. Select an unused file (9 to 255) to store channel status information.
SLC Communication Channels 13-59 Table 13.17 Define these parameters when configuring a SLC 5/03, 5/04, or 5/05 processor as a master station using standard polling mode to communicate with slave stations (Continued) Tab Parameter Default Selections Polling Mode Message Based If you want to receive: • only one message from a slave station per its turn, choose STANDARD (SINGLE MESSAGE TRANSFER PER NODE SCAN). Choose this method only if it is critical to keep the poll list scan time to a minimum.
13-60 SLC Communication Channels Table 13.17 Define these parameters when configuring a SLC 5/03, 5/04, or 5/05 processor as a master station using standard polling mode to communicate with slave stations (Continued) Tab Parameter Default Selections Normal Polling Range – High 0 Select the last slave station address to normal poll. Normal Polling Range – Low 255 Select the first slave station address to normal poll. Entering 255 disables normal polling.
SLC Communication Channels 13-61 Minimum DF1 Half-duplex Master Channel 0 ACK Timeout The governing timeout parameter to configure for a DF1 Half-duplex Master is the channel 0 ACK Timeout. The ACK Timeout is the amount of time you want the processor to wait for an acknowledgment of its message transmissions.
13-62 SLC Communication Channels Determining Minimum Master ACK Timeout To determine the minimum ACK Timeout, you must first calculate the transmission time by multiplying the maximum sized data packet for your processor by the modem rate in ms/byte. For an example we will assume an SLC 5/03 processor (103 data words or 224 bytes total packet size including overhead) and a 9600 bps modem, which transmits at approximately 1 ms/byte. Therefore, the message transmission time is 224 ms.
SLC Communication Channels 13-63 Table 13.19 Sum of the Transmission Rates Parameter Example Values (in ms) modem turnaround time 50 calculated ACK Timeout 304 round up to nearest 20 ms 320 Monitor Active Stations To see what stations are active, view the channel 0 active node table in the SLC 5/03, SLC 5/04, or SLC 5/05 processor status file (S:67/0-S:82/15). Each bit in the file represents a station on the link.
13-64 SLC Communication Channels Message-based communication should also be used in redundant SLC master station systems implemented with the 1746-BSN backup communication module. With message-based mode, you do not have an active node file that you can use to monitor station status. Also, you cannot implement slave station-to-slave station messaging.
SLC Communication Channels 13-65 1. On the Channel 0 tab, choose DF1 Half-Duplex Master for your Driver. 2. Choose a Message-based Polling Mode. 3. Configure the communication driver characteristics according to Table 13.20.
13-66 SLC Communication Channels Table 13.20 Define these parameters when configuring a SLC 5/03, 5/04, or 5/05 processor as a master station using message-based polling mode to communicate with slave stations. Tab Parameter Default Selections General Diagnostic File 0 SLC 5/03 (OS 302, Series C or higher), SLC 5/04 (OS 401, Series C or higher) and SLC 5/05 only. Select an unused file (9-255) to store channel status information.
SLC Communication Channels 13-67 Table 13.20 Define these parameters when configuring a SLC 5/03, 5/04, or 5/05 processor as a master station using message-based polling mode to communicate with slave stations.
13-68 SLC Communication Channels DF1 Half-duplex Master Channel Status Channel Status data is stored in the diagnostic file defined on the Channel 0 Configuration screen. See Table 13.21 on page 13-68 for information regarding the diagnostic counter data displayed. Double-click on the Channel Status Icon Located beneath the Configuration icon to bring up the Channel Status screen. See Table 13.21 for details concerning the DF1 Half-Duplex Master Channel Status Screen. Table 13.
SLC Communication Channels 13-69 Table 13.
13-70 SLC Communication Channels Define the location of the diagnostic file used for Channel Status here. For Channel Status details, see page 13-74. 1. On the Channel 0 tab, choose DF1 Half-Duplex Slave for your Driver. 2. Configure the communication driver characteristics according to Table 13.22.
SLC Communication Channels 13-71 Table 13.22 Define these parameters when configuring a SLC 5/03, 5/04, or 5/05 processor as a slave station. Tab Parameter Default Selections General Diagnostic File 0 SLC 5/03 (OS 302, Series C or higher), SLC 5/04 (OS 401, Series C or higher) and SLC 5/05 only. Select an unused file (9 to 255) to store channel status information. You must define a diagnostic file in order to be able to view channel 0 status. See Table 13.23 on page 13-74 for a file description.
13-72 SLC Communication Channels Table 13.22 Define these parameters when configuring a SLC 5/03, 5/04, or 5/05 processor as a slave station. (Continued) Tab Parameter Default Selections Error Detection CRC With this selection, you choose the how the processor checks the accuracy of each DF1 packet transmission. BCC: This algorithm provides a medium level of data security. It cannot detect: • transposition of bytes during transmission of a packet.
SLC Communication Channels 13-73 Table 13.22 Define these parameters when configuring a SLC 5/03, 5/04, or 5/05 processor as a slave station. (Continued) Tab Parameter Default Selections Message Retries 3 Defines the number of times a slave station resends its message to the master station before the slave station declares the message undeliverable.
13-74 SLC Communication Channels DF1 Half-duplex Slave Channel Status Channel Status data is stored in the diagnostic file defined on the Channel 0 Configuration screen. See Table 13.23 for information regarding the diagnostic counter data displayed. Double-click on the Channel Status Icon Located beneath the Configuration icon to bring up the Channel Status screen. See Table 13.23 for details concerning the DF1 Half-Duplex Slave Channel Status Screen. Table 13.
SLC Communication Channels 13-75 Table 13.
13-76 SLC Communication Channels DF1 Radio Modem Communications Processors running OS Series C FRN 6 and higher firmware include a new channel 0 system mode driver called DF1 Radio Modem. This driver implements a protocol, optimized for use with radio modem networks, that is a hybrid between DF1 Full-duplex protocol and DF1 Half-duplex protocol, and therefore is not compatible with either of these protocols.
SLC Communication Channels 13-77 For modern serial radio modems that support full-duplex data port buffering and radio transmission collision avoidance, the DF1 Radio Modem driver can be used to set up a masterless peer-to-peer radio network, where any node can initiate communications to any other node at any time, as long as all of the nodes are within radio range so that they receive each other’s transmissions.
13-78 SLC Communication Channels • Can I take advantage of the SLC 5/03, 5/04, and 5/05 channel-to-channel passthru to remotely program the other SLC nodes using RSLinx and RSLogix 500 running on a PC connected to a local SLC processor via DH-485, DH+ or Ethernet? Yes, with certain limitations imposed based on the radio modem network. See the following chapter for more passthru details and limitations when using the DF1 Radio Modem driver.
SLC Communication Channels 13-79 1. On the Channel 0 tab, choose DF1 Radio Modem for your Driver. 2. Configure the communication driver characteristics according to Table 13.24. Table 13.24 Define these communication parameters when configuring a SLC 5/03, 5/04, or 5/05 processor for DF1 Radio Modem communication. Tab Parameter Default Selections General Diagnostic File 0 Select an unused file (9 to 255) to store channel status information.
13-80 SLC Communication Channels Table 13.24 Define these communication parameters when configuring a SLC 5/03, 5/04, or 5/05 processor for DF1 Radio Modem communication. (Continued) Tab Parameter Default Selections Chan. 0 System Control Line No Handshaking This parameter defines the mode in which the driver operates. Choose a method appropriate for your system’s configuration. • If you are not using a modem, choose NO HANDSHAKING.
SLC Communication Channels 13-81 DF1 Radio Modem Channel Status Channel Status data is stored in the diagnostic file defined on the Channel 0 Configuration screen. See Table 13.25 for information regarding the diagnostic counter data displayed. Double-click on the Channel Status Icon Located beneath the Configuration icon to bring up the Channel Status screen. See Table 13.25 for details concerning the DF1 Radio Modem Channel Status Screen.
13-82 SLC Communication Channels Table 13.
SLC Communication Channels 13-83 Figure 13.13 Applying DF1 Radio Modem Protocol (2nd Rebroadcast) REPLY 1 Note 4 (1st Rebroadcast) REPLY 1 Node 1 No Bits Note 1 CMD 1 (DST = 4, SRC = 1) Node 2 Node 3 1, 3, 4 1, 2, 4 CMD1 (1st Rebroadcast) Note 2 Note 3 REPLY 1 (DST = 1, SRC = 4) Node 4 No Bits CMD 1 (2nd Rebroadcast) Note 1 – The link layer of Node 1 blocks the re-transmission of a packet that is received with the SRC byte equal to the receiving node’s station address.
13-84 SLC Communication Channels Using Modems that Support DF1 Communication Protocols The types of modems that you can use with SLC processors include dial-up phone modems, leased-line modems, radio modems and line drivers. For point-to-point full-duplex modem connections, use DF1 Full-duplex protocol. For radio modem connections, use DF1 Radio Modem. For general point-to-multipoint modem connections, use DF1 Half-duplex Master and Slave protocols.
SLC Communication Channels 13-85 Radio Modems Radio modems may be implemented in a point-to-point topology supporting either half-duplex or full-duplex communications, or in a point-to-multipoint topology supporting half-duplex communications between three or more modems. In the point-to-point topology using full-duplex radio modems, configure the SLC processors for DF1 Full-duplex protocol.
13-86 SLC Communication Channels Modem Control Line Operation in SLC 5/03, SLC 5/04 and SLC 5/05 Processors The following sections explain the operation of the SLC 5/03, SLC 5/04, and SLC 5/05 modem control when you configure the RS232 channel for a particular modem handshaking method.
SLC Communication Channels 13-87 Transmission requires all three inputs (CTS, DCD, and DSR) to be active. Whenever DSR and DCD are both active, the modem lost bit is reset. Half-duplex Modem without Continuous Carrier Selected - This is exactly the same as Half-duplex Modem with Continuous Carrier except monitoring of DCD is not performed. DCD is still required for receptions but is not required for transmissions. Transmissions still require CTS and DSR.
13-88 SLC Communication Channels DF1 Radio Modem When you configure the SLC 5/03, SLC 5/04, and SLC 5/05 processors for DF1 Radio Modem, the following control line operation takes effect: No Handshaking Selected - DTR is always active and RTS is always inactive. Receptions and transmissions take place regardless of the states of DSR, CTS, or DCD inputs. This selection should only be made when the processor is directly connected to another DTE device.
SLC Communication Channels 13-89 Full Duplex Modem - DTR and RTS are always active except at the following times. If DSR goes inactive, modem lost bit (S:5/14) is turned on immediately. While DSR is inactive, neither reception nor transmission is performed. The processor does not monitor DCD. Transmission requires CTS & DSR inputs to be active. .
13-90 SLC Communication Channels Modbus RTU Protocol This section shows the configuration parameters for Modbus RTU (Remote Terminal Unit transmission mode) protocol. For more information about the Modbus RTU protocol, see the Modbus Protocol Specification (available from http://www.modbus.org). SLC 5/03, SLC 5/04, and SLC 5/05 support Modbus RTU Master from Series C FRN11 onwards.
SLC Communication Channels IMPORTANT 13-91 Modbus protocol may not be consistently implemented in the field. The Modbus specification calls for the addressing range to start at 1; however, some devices start addressing at 0. The Modbus Data Address in the Message Setup Screen may need to be incremented by one to properly access a Modbus slave’s memory, depending on that slave’s implementation of memory addressing.
13-92 SLC Communication Channels Define the location of the diagnostic file used for Channel Status here. For Channel Status details, see page 13-94. Select the Modbus RTU Master from the Channel Configuration menu as shown below.
SLC Communication Channels 13-93 The Baud defaults to 19200. The Control Line can be configured as: • No Handshaking • Full-Duplex Modem • Half Duplex without Continuous Carrier The Protocol Control defaults are: • No Handshaking • InterChar. Timeout = 0 • Pre Transmit Delay = 0. When the system driver is Modbus RTU Master, the following communication port parameters can be changed: Table 13.
13-94 SLC Communication Channels Modbus RTU Master Channel Status Channel Status data is stored in the diagnostic file defined on the Channel 0 Configuration screen. Double-click on the Channel Status Icon Located beneath the Configuration icon to bring up the Channel Status screen. The Channel Status dialog box similar to the following appears. Data for the data link layer diagnostic counters is displayed. See Table 13.27 for information regarding the diagnostic counter data displayed.
SLC Communication Channels 13-95 Table 13.
13-96 SLC Communication Channels Table 13.
SLC Communication Channels 13-97 Modbus Error Codes Upon receiving a Modbus command that is not supported or improperly formatted, the controller configured for Modbus RTU Master will respond with one of the exception codes listed in the following table: Table 13.30 Modbus Error Codes in Modbus RTU Master MSG Instruction Error Code Error Description Received Exception Code 81 Illegal Function The function code sent by the Master is not supported by the slave 1 or has an incorrect parameter.
13-98 SLC Communication Channels ASCII Communications The SLC 5/03 (OS301 and higher), SLC 5/04, and SLC 5/05 processors support user-defined ASCII protocol by configuring channel 0 for User mode. In User mode, all received data is placed in a buffer. To access the data, use the ASCII instructions in your ladder program. You can also send ASCII string data to most attached devices that accept ASCII protocol. TIP Only ASCII instructions can be used when User mode is configured.
SLC Communication Channels 13-99 Select User Mode 1. On the Channel 0 user tab, choose ASCII for your Driver. 2. Configure the communication driver characteristics according to Table 13.31.
13-100 SLC Communication Channels Table 13.31 Define these communication parameters when configuring an SLC 5/03, SLC 5/04, or SLC 5/05 processor for ASCII communication. Tab Parameter Default Selections Channel 0 User Baud Rate 19200 Toggles between the communication rate of 110, 300, 600, 1.2K, 2.4K, 4.8K, 9.6K and 19.2K (additional rate of 38.4K for SLC 5/04 and SLC 5/05 only). Parity None Toggles between None, Odd, and Even. Stop Bits 1 Toggles between 1, 1.5, and 2.
Chapter 14 SLC Passthru Communications There are three types of communications passthru (or bridging) supported by SLC 5/03, SLC 5/04 and SLC 5/05 processors. • Remote I/O passthru via the 1747-SN and 1747-BSN remote I/O scanner modules • DeviceNet passthru via the 1747-SDN DeviceNet scanner module • Channel-to-channel passthru The following table summarizes the processor OS firmware/passthru capability. Table 14.
14-2 SLC Passthru Communications IMPORTANT DeviceNet Passthru Remote I/O passthru uses buffer number 32 in the M0 and M1 files of the remote I/O scanner module. Avoid using these buffers for block transfer read/write instructions if you intend to use the remote I/O passthru capability. DeviceNet passthru allows the SLC processor system to act as a bridge between the channel 0 or channel 1 network, and the DeviceNet network supported by the 1747-SDN DeviceNet scanner module.
SLC Passthru Communications 14-3 processor communications during end-of-scan. In program mode, the processor continuously services communications including passthru. TIP Channel-to-channel passthru only works for single hop bridging. One end node must be connected to the channel 0 network and the other end node must be connected to the channel 1 network. The channel 1 passthru link ID must match the network link ID of the end node connected on the channel 1 network.
14-4 SLC Passthru Communications destination equal to 128 plus the processor’s channel 1 network address are kept and executed by the passthru processor. DF1 Half-duplex Master packets received with a destination address outside of the valid channel 1 address range are rebroadcast as slave-to-slave messages. DF1 Radio Modem packets received with a destination address outside of the valid channel 1 address range are ignored.
SLC Passthru Communications TIP 14-5 The SLC 500 Fixed, SLC 5/01, SLC 502, ControlLogix, FlexLogix, and CompactLogix controllers can only respond to local DH-485 packets. Set S34/6=1 when using SLC 5/03 channel-to-channel passthru to communicate with the SLC 500 Fixed, SLC 5/01, SLC 502, ControlLogix, FlexLogix, and CompactLogix controllers via DH-485 on channel 1. The Local Passthru Queue Full bit is a monitor only bit that is set to a one anytime this 30-slot local passthru queue becomes full.
14-6 SLC Passthru Communications When channel 0 is configured for DF1 Full-duplex and S:34/5=1, the SLC 5/03 passthru processor can be used by RSLinx to go online through channel 0 to the channel 1 DH-485 network. The RSLinx RS-232 DF1 driver is used, with Device configured for 1770-KF3/1747-KE. Remember to set S:34/6=1 if attempting to browse or go online with SLC 500 fixed, SLC 5/01, SLC 5/02, ControlLogix, FlexLogix, and/or CompactLogix controllers on DH-485.
SLC Passthru Communications 14-7 DH-485 with S:34/0=0 or for DF1 Full-duplex with S:34/5=1, then a ‘+’ sign will appear to the left of the SLC 5/03 icon. Clicking on the ‘+’ sign will expose a DH-485 or DF1 network underneath the SLC 5/03 icon. Clicking on the ‘+’ sign to the left of the DH-485 or DF1 network will result in RSWho browsing for nodes 0 to 31 on the DH-485 network or for node 1 on the DF1 network.
14-8 SLC Passthru Communications Using RSLinx Classic, version 2.50 and higher, with SLC 5/04 Passthru RSLinx Classic, version 2.42 and below, only supports DF1 Full-duplex to DH+, DF1 Half-duplex Master to DH+, DH-485 to DH+, DH+ to DF1 Full-duplex, and DH+ to DH-485 passthru. RSLinx Classic, version 2.43 supports all modes of channel-to-channel passthru described below, except when channel 0 control line handshaking is enabled. RSLinx Classic, version 2.
SLC Passthru Communications 14-9 1784-KT, -KTX(D), -PKTX(D), or –PCMK card. When RSWho is browsing the SLC 5/04 on DH+, and channel 0 is either configured for DH-485 with S:34/0=0 or for DF1 with S:34/5=1, then a ‘+’ sign will appear to the left of the SLC 5/04 icon. Clicking on the ‘+’ sign will expose a DH-485 or DF1 network underneath the SLC 5/04 icon.
14-10 SLC Passthru Communications Access to the passthru routing table is located under the channel configuration selection in RSLogix 500 Programming Software. If a Passthru Routing Table File number was entered in the General Tab in the Channel Configuration dialog box, click on the + in front of Channel Configuration to reveal the routing table selection. Double-click on Routing Table to view and modify the passthru routing table.
SLC Passthru Communications IMPORTANT 14-11 Only Ethernet devices that support Client Server Protocol (CSP), such as SLC 5/05 processors, PLC-5 processors, PLC-5 Ethernet sidecars (1785-ENET), and RSLinx software, can use SLC 5/05 passthru. Passthru does not work with Ethernet devices supporting only EtherNet/IP protocol. Using RSLinx Classic, version 2.50 and higher, with SLC 5/05 Passthru RSLinx Classic, version 2.
14-12 SLC Passthru Communications exceed the number of available outgoing connections. The passthru processor will show up on the RSWho browse at node 128. When channel 0 is configured for DH-485 and S:34/0=0, the SLC 5/05 passthru processor can be used by RSLinx to go online through channel 0 to the channel 1 Ethernet network, as long as the PC running RSLinx is directly connected to the DH-485 network through a 1784-KTX(D), -PKTX(D), or – PCMK card.
SLC Passthru Communications 14-13 SLC 5/05 Passthru Error Codes A SLC 5/05 passthru processor may respond to a MSG instruction or RSLinx with an error code of 20H under the following conditions. • The routing table integer file number is out of range (9 to 255). • The routing table file does not exist in the user program directory or is less than 2 word elements in length. • The IP address entry in the routing table does not exist. • Lack of available connections.
14-14 SLC Passthru Communications 4. When you run RSWho on that passthru processor network, the SLC 5/03, 5/04, or 5/05 passthru processor should appear with a ‘+’ sign to the left of its icon as shown below: Figure 14.1 SLC 5/04 Passthru Processor on RSWho 5. Click on the ‘+’ sign and verify that a Channel 0, DF1 network appears below the SLC 5/04 (or SLC 5/03 or 5/05), as shown below: Figure 14.
SLC Passthru Communications 14-15 6. Check Browse only the specified addresses: and specify the low and high addresses of the range to be browsed: Figure 14.3 Configuring RSWho Browse Addresses 7. Click on the Advanced Browse Settings tab, check the Use custom browse settings box and enter 1 for the Maximum concurrent packets to this network: Figure 14.
14-16 SLC Passthru Communications If channel 0 is configured for DF1 Half-duplex Master, then the RSWho Poll Timeout should be set to: Channel 0 ACK Timeout * [1+ (2 * channel 0 message retries)] If channel 0 of an SLC 5/05 is configured for DF1 Radio Modem, then the RSWho Poll Timeout should be set the same as the Ethernet channel 1 MSG Reply Timeout. The RSWho Poll Timeout for known stations should be set to the time it takes to poll the entire range of addresses.
Chapter 15 Messaging Examples The purpose of this chapter is to illustrate some of the more common but elaborate messaging examples using the SLC 500 processors. Not all examples will appear with a full detailed step by step procedure necessary. Step by Step procedures are available for all of the examples in KnowledgeBase Documents at the following website: http://support.rockwellautomation.
15-2 Messaging Examples IMPORTANT Remote Terminology In a multi-network environment, each network must have a unique Link ID (Pass Thru Link ID) for help in obtaining acceptable results. Remote Bridge Address Remote Bridge Address is the remote node address of the bridge device used to connect two networks together. TIP SLC Fixed Processors, SLC 5/01 and SLC 5/02 are all non-remote MSG capable processors.
Messaging Examples TIP 15-3 Link ID’s are modified in each processors Channel Configuration properties. The default Passthru Link ID for the SLC 5/03, 5/04 and 5/05 processors channel 0 port is 1. The default Passthru Link ID for the SLC 5/03, 5/04 and 5/05 processors channel 1 port is 2. Refer to Chapter 14 for more information regarding passthru. SLC 5/03 Passthru Examples Passthru Example: DF1 to DH-485 The following illustrates a SLC 5/03 processor as a passthru processor.
15-4 Messaging Examples The DF1 Remote/Local Pass-Thru bit (S2:34/6) is cleared in order to send messages to the channel 1 DH-485 network as remote DH-485 packets. This is the default setting for this bit. The DF1 Remote/Local Pass-Thru bit (S2:34/6) is needed when non-remote capable devices exist on the channel 1 DH-485 network, such as SLC 500 Fixed, SLC 5/01, SLC 5/02, ControlLogix, FlexLogix, and CompactLogix controllers.
Messaging Examples 15-5 The following is the ladder logic necessary for the SLC 5/04 processor. The following is the MSG setup for the SLC 5/04 processor. The type of MSG instruction is Local. The local node address is the node number of the destination DH-485 address. For the step by step procedure for this example, refer to Knowledgebase Document Number: G63635969.
15-6 Messaging Examples Passthru Example: DH-485 to DF1 The following illustrates a SLC 5/03 processor as a passthru processor that receives remote messages targeting the SLC 5/04 on the DF1 network. The SLC 5/03 processor will forward remote messages received on the DH-485 network (channel 1) to the DF1 network (channel 0) as local messages. For this example, the SLC 5/03’s configuration bits are set to the following values.
Messaging Examples TIP 15-7 No programming logic is necessary in the passthru processor. The following is the ladder logic necessary for the SLC 5/03 processor (node 2). The following is the MSG Setup for the SLC 5/03 processor (node 2).
15-8 Messaging Examples The type of MSG instruction is Remote. Local Bridge Address is the node number of the passthru DH-485 processor. Remote Bridge Address is not required. Remote Station Address is the node number of the target processor. A DF1 Full-duplex target device does not require a Remote Station Address. Remote Bridge Link ID is the Link ID number of the DF1 destination network. For the step by step procedure for this example, refer to Knowledgebase Document Number: G63059559.
Messaging Examples 15-9 Passthru Example: DH-485 to DH-485 The following illustrates a SLC 5/03 processor as a passthru processor when both channel’s networks are configured for DH-485. The SLC 5/03 processor will forward remote messages received on the DH-485 network (channel 1) to the DH-485 network (channel 0) as remote messages. For this example, the SLC 5/03’s configuration bits are set to the following values.
15-10 Messaging Examples TIP No programming logic is necessary in the passthru processor. The following is the ladder logic necessary for the SLC 5/03 processor (node 2). The following is the MSG Setup for the SLC 5/03 processor (node 2). The type of MSG instruction is Remote.
Messaging Examples 15-11 Local Bridge Address is the node number of the passthru DH-485 processor. Remote Bridge Address is not required if the target device is remote capable. Remote Station Address is the node number of the target processor. Remote Bridge Link ID is the Link ID number of the destination network. The SLC 5/04 processor (node 15) is also capable of messaging to the SLC 5/03 (node 2). The following MSG setup information would be required in the SLC 5/04 MSG instruction.
15-12 Messaging Examples SLC 5/04 Passthru Examples Passthru Example: DF1 to DH+ The following illustrates a SLC5/03 sending a local message via DF1 (CH0) to a SLC5/04 processor. The SLC5/04 processor that receives the initial message will send the message out DH+ to the SLC5/04 processor whose address matches the Local Bridge Address on the DH+ network as long as DF1 Passthru is enabled. 1747-CP3 cable is used to connect the SLC5/03 CH0 port to the SLC5/04 CH0 port.
Messaging Examples 15-13 The following is the ladder logic necessary for the SLC5/03 processor. MSG Instruction The following rung triggers the MSG instruction with a true-to-false transition upon entering into the run mode. Each time the MSG instruction either reaches Error or Done, rung 2:1 unlatches the enable bit, giving the instruction a false-to-true transition the next scan.
15-14 Messaging Examples The following is the Channel Configuration MSG Setup for the SLC5/03 processor. Channel 0 Mode is set for System. Chan. 0 - System driver is set for DF1 Full Duplex. For the step by step procedure for this example, refer to Knowledgebase Document Number: G20023.
Messaging Examples 15-15 Passthru Example: DH+ to DF1 For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20024.
15-16 Messaging Examples Passthru Example: DH-485 to DH+ For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20025.
Messaging Examples 15-17 Passthru Example: DH+ to DH-485 For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20026.
15-18 Messaging Examples SLC 5/05 Passthru Examples Passthru Example: DF1 to Ethernet The IP Addresses used in the following illustration are for example purposes only. Contact your system administrator for IP addresses unique to your network. In the following diagram, a SLC 5/03 will send a local message via DF1 to the SLC 5/05 (IP Address 100.100.115.9). The SLC 5/05 acts as a bridge, sending the message out via Ethernet to the SLC 5/05 (IP Address 100.100.115.
Messaging Examples 15-19 The following is the logic necessary for the SLC5/03 processor. MSG Instruction The following rung triggers the MSG instruction with a true-to-false transition upon entering into the run mode. Each time the MSG instruction either reaches Error or Done, rung 2:1 unlatches the enable bit, giving the instruction a false-to-true transition the next scan.
15-20 Messaging Examples Local node address is the station address in the SLC 5/05 (IP Address 100.100.115.9) routing table where the target IP address for SLC 5/05 (IP Address 100.100.115.1) is stored. SLC 5/05 (IP Address 100.100.115.9) Bridge Ladder logic is not required for the SLC 5/05 which acts as the bridge from DF1-to-Ethernet. However, you must set up a passthru routing table when configuring the bridge.
Messaging Examples 15-21 The Passthru Routing Table File is the integer file used by the processor to store routing table IP addresses and link them to unique node addresses. IMPORTANT Channel 0 Source ID must be set to 0 when SLC 5/05 (IP Address 100.100.115.9) is used as the bridge between DF1 full-duplex and Ethernet. Passthru Routing Table The passthru routing table is located under the channel configuration selection in RSLogix 500 Programming Software.
15-22 Messaging Examples Passthru Example: Ethernet to DF1 For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20028.
Messaging Examples 15-23 Passthru Example: DH-485 to Ethernet For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20029.
15-24 Messaging Examples Passthru Example: Ethernet to DH-485 For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20030.
Messaging Examples Remote Examples 15-25 All of the following remote examples were constructed for the following network.
15-26 Messaging Examples Network Message Example: SLC 5/04 to SLC 5/02 via DHRIO and KA5 For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20031.
Messaging Examples 15-27 Network Message Example: SLC 5/04 to SLC 5/03 via DHRIO and KA5 For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20032.
15-28 Messaging Examples Network Message Example: SLC 5/04 to SLC 5/04 via DHRIO For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20033.
Messaging Examples 15-29 Network Message Example: SLC 5/04 to SLC 5/02 via KA5 For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20034.
15-30 Messaging Examples Network Message Example: SLC 5/04 to SLC 5/03 via KA5 For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20035.
Messaging Examples 15-31 Network Message Example: SLC 5/04 to SLC 5/05 via DHRIO and ENET For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20036.
15-32 Messaging Examples Network Message Example: SLC 5/05 to SLC 5/04 via ENET and DHRIO For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20037.
Messaging Examples 15-33 Network Message Example: SLC 5/05 to SLC 5/03 via ENET, CNB and KFC For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20038.
15-34 Messaging Examples Network Message Example: SLC 5/05 to SLC 5/03 via ENET, DHRIO and KA5 For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20039.
Messaging Examples 15-35 Network Message Example: PLC 5/20E to SLC 500 CH0 via ENI For the Step by Step procedure for this example refer to Knowledgebase Document Number: G20040.
15-36 Messaging Examples Notes: Publication 1747-RM001G-EN-P - November 2008
Chapter 16 Troubleshooting Faults This chapter lists the major error fault codes, indicates the probable causes of faults, and recommends corrective action. This chapter also explains the operating system download faults for the SLC 5/03 (and higher) processors. Automatically Clear Faults The following section describes the different ways to automatically clear a fault using your programming software.
16-2 Troubleshooting Faults Manually Clear Faults The following section describes the different ways to manually clear a fault when using an SLC processor. • Manually clear the major fault bit S:1/13, and the minor and major error bits S:5/0-7 in the status file, using a programming device or a Data Table Access Module. Place the processor in the REM Program mode. Correct the condition causing the fault, then return the processor to either REM Run or any of the REM Test modes.
Troubleshooting Faults SLC Processor Faults 16-3 The processor faults are divided into the following types. • • • • Powerup errors Going-to-run errors Run errors User program instruction errors Powerup Errors Table 16.1 Powerup Errors Error Code (Hex) Description 0001 NVRAM error. Probable Cause Recommended Action • Either noise, • lightning, • improper grounding, • lack of surge suppression on outputs with inductive loads, or Correct the problem, reload the program, and run.
16-4 Troubleshooting Faults Table 16.1 Powerup Errors Error Code (Hex) Description Probable Cause Recommended Action 0008 Internal software error. An unexpected software error occurred due to: Correct the problem, reload the program, and run. You can use the autoload feature with a memory module to automatically reload the program and enter the Run mode. If the problem re-occurs, contact your RSI representative.
Troubleshooting Faults 16-5 Table 16.2 Going-to-Run Errors (Continued) Error Code (Hex) Description 0012 The ladder program has a memory error. Probable Cause Recommended Action • Either noise, • lightning, • improper grounding, • lack of surge suppression on outputs with inductive loads, or Correct the problem, reload the program, and run. If the error persists, be sure to use current RSI programming software to develop and load the program. • poor power source.
16-6 Troubleshooting Faults Table 16.2 Going-to-Run Errors (Continued) Error Code (Hex) Description Probable Cause Recommended Action 0018 Incompatible user program. Operating system type mismatch. This error can also occur during powerup. The user program is too advanced to be executed in the current operating system. Contact your your local Rockwell Automation representative to purchase an upgrade kit for your processor. 0019 A duplicate label number was detected.
Troubleshooting Faults 16-7 Table 16.3 Run Errors (Continued) Error Code (Hex) Description Probable Cause 0021 A remote power failure of an expansion I/O chassis has occurred. Fixed and FRN 1 to 4 SLC 5/01 Fixed in FRN 1 to 4 SLC 5/01 processors: Cycle power on the local processors: Power was removed or the power dipped below specification chassis. for an expansion chassis.
16-8 Troubleshooting Faults Table 16.3 Run Errors (Continued) Error Code (Hex) Description Probable Cause Recommended Action 0025 Excessive stack depth/JSR calls for the STI routine. A JSR instruction is calling for a file number assigned to an STI routine. Correct the user program to meet the requirements and restrictions for the JSR instruction, then reload the program and run. 0026 Excessive stack depth/JSR calls for an I/O interrupt routine.
Troubleshooting Faults 16-9 Table 16.3 Run Errors (Continued) Error Code (Hex) Description Probable Cause Recommended Action 002D An invalid referenced indirect address subelement exists. Either a subelement is referenced incorrectly or an indirect reference has been made to an M-file. Correct the references and try again. 002E Invalid DII Input slot. The referenced slot is empty or a non-discrete I/O card is present. Change the input slot to a discrete I/O card.
16-10 Troubleshooting Faults Table 16.4 User Program Instruction Errors (Continued) Error Code (Hex) Description Probable Cause Recommended Action 0034 A negative value for a timer accumulator or preset value was detected. Fixed processors with 24 VDC input only: A negative or zero HSC preset was detected in a HSC instruction. The accumulated or preset value of a timer in the user program was detected as being negative.
Troubleshooting Faults 16-11 I/O Errors ERROR CODES: The characters xx in the following codes represent the slot number, in hexadecimal. If the exact slot cannot be determined, the characters xx become 03 for fixed controllers and 1F for modular controllers. Refer to the table below. Table 16.
16-12 Troubleshooting Faults Table 16.6 I/O Errors Error Code (Hex) Description xx50 A chassis data error is detected. Probable Cause • Either noise, • lightning, Recommended Action Correct the problem, clear the fault, and re-enter Run mode. • improper grounding, • lack of surge suppression on outputs with inductive loads, or • poor power source. xx51 A “stuck” runtime error is detected on an I/O module. If this is a discrete I/O module, this is a noise problem.
Troubleshooting Faults 16-13 Table 16.6 I/O Errors (Continued) Error Code (Hex) Description Probable Cause Recommended Action xx56 The chassis configuration specified in the user program is detected as being incorrect. The chassis configuration specified by Correct the chassis configuration, the user does not match the hardware. reload the program and run. xx57 A specialty I/O module has not responded to a Lock Shared Memory command within the required time limit.
16-14 Troubleshooting Faults Table 16.6 I/O Errors (Continued) Error Code (Hex) Description Probable Cause Recommended Action xx90 Interrupt problem on a disabled slot. A specialty I/O module requested service while a slot was disabled. Refer to the user manual for the specialty I/O module. You may have to replace the module. xx91 A disabled slot has faulted. A specialty I/O module in a disabled slot has faulted. Cycle chassis power.
Troubleshooting Faults Troubleshoot SLC 5/03 and Higher Processors 16-15 Between the time you apply power to the processor, and it has a chance to establish communication with a connected programming device, the only form of communication between you and the processor is through the LED display. Powerup LED Display When power is applied, all the LEDs flash on momentarily and then off. This is part of the normal power-up sequence.
16-16 Troubleshooting Faults The following table describes the possible LED combinations that are displayed every other time the LEDs flash on. Table 16.7 LED Combinations ON LED Display Description FAULT, FORCE, DH-485, DH+, or Ethernet Fatal hardware error exists. FAULT, FORCE, RS232, DH-485 or DH+ A hardware watchdog timeout exists. FAULT, BATT NVRAM error exists. FAULT, BATT, RS232 The contents of the operating system memory module are corrupt.
Appendix A SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History OS300, Series A, FRN 1 released: June 1993 Original Release OS300, Series A, FRN 2 released: July 1993 Enhancements OS300, Series A, FRN 3 released: March 1994 Enhancements None • On-Line Editing Several changes were made to the On-Line Editing sub-system to decrease the impact to scan time. • Instruction Performance The IOM, JMP, JSR and OSR instructions have been modified to enhance performance.
A-2 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History OS301, Series A, FRN 5 released: August 1994 Enhancements • ASCII Instructions The ASCII instructions ABL, ACB, ACI, ACL, ACN, AEX, AHL, AIC, ARD, ARL, ASC, ASR, AWA, and AWT are supported in this release. The STRING and ASCII data types are also supported.
SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History OS400, Series A, FRN 1 released: August 1994 Original Release OS301, Series A, FRN 6 OS400, Series A, FRN 2 released: November 1994 Enhancements OS301, Series A, FRN 7 0S400, Series A, FRN 3 released: March 1995 Enhancements A-3 None • Selection of number of data bits and stop bits with generic ASCII communications added The Generic ASCII protocol has been expanded to allow 7 or 8 data bits and 1, 1.5, or 2 stop bits.
A-4 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History OS301, Series A, FRN 8 OS400, Series A, FRN 4 released: April 1995 Enhancements OS302, Series A, FRN 9 OS401, Series A, FRN 5 released: December 1995 Enhancements None • Indirect Addressing Allows for simplified programming. • Trigonometric and Exponential Math Functions Includes SIN, COS, TAN, ASN, ACS, ATN, LN, LOG, ABS, DEG, RAD, and XPY. • Compute (CPT) Instruction Allows for complex math computations.
SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History A-5 • Remote I/O (RIO) Passthru via a 1747-SN Scanner Module (OS401 only) Allows an SLC 5/04 processor to act as a bridge between DH+ and RIO. Remote I/O passthru also supports uploads/downloads of applications to RIO devices. • Program Memory of 12K, 28K, or 60K words and 4K of additional data words (OS401 only) Offers a variety of modular processors that fit a variety of memory requirements.
A-6 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History OS500, Series A, FRN 1 released: October 1997 Original Release OS302, Series B, FRN 11 OS401, Series B, FRN 8 OS500, Series A, FRN 2 released: November 1997 Enhancements OS302, Series B, FRN 12 released: November 1998 OS401, Series B, FRN 9 released: July, 1999 OS501, Series A, FRN 3 released: July 1998 Enhancements (OS501 only) OS302, Series B, FRN 12 released: November 1998 OS401, Series B, FRN 9 released: July 1999 OS501
SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History A-7 In the previous release, it took 60 μsec when saving interrupt information at the end of scan. This has been improved to 40 μsec.
A-8 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History instruction moves the current value of the 10uS free running clock into the destination address. If it is an integer address, it only moves the least 16 bits into the address. If it is a float address, it converts the long integer value into a float and moves it to the relative address. After the free running clock reaches 0xfffff value (10.4857 sec), it will wrap around to 0 and continues incrementing.
SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History A-9 permissible for the control block to take up User Ladder Program space as well as use additional user memory for storing runtime ramp information that is not user accessible. • File Bit Comparison Instruction (FBC) and Diagnostic Detect Instruction (DDT) The FBC and DDT diagnostic instructions are output instructions that you can use to monitor machine or process operations to detect malfunctions.
A-10 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History • Message Error Code (OS501 only) After a Unix Server has defined the unsolicited “Client” IP address in SLC 5/05, the Server is removed from the network. The SLC 5/05 “Client” messages continue to be initiated since the user program re-triggers them on a message error.
SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History A-11 (BSD) that has been in use since the development of the PLC-5 Ethernet over eight years ago. This stack was also ported over to the legacy Ethernet products to let us take advantage of any bug fixes we did not pickup over the years, enhanced UDP message support and the ability to do super-netting.
A-12 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History OS302, Series C, FRN 5 OS401, Series C, FRN 5 OS501, Series C, FRN 5 released: October 2001 Enhancements • Additional Ethernet connections for 32k and 64k processors (OS501 only) The total number of available Ethernet connections has increased by eight from 16 to 24 in the 32k (L552) and 64k (L553) SLC 5/05 processors.
SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History OS302, Series C, FRN 6 OS401, Series C, FRN 6 OS501, Series C, FRN 6 released: November 2002 A-13 Enhancements • Response support for additional PLC-5 style commands SLC 5/03, 5/04 and 5/05 processors now can receive and respond to the following additional PLC-5 style commands received through channel 0 or channel 1.
A-14 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History coordinate a timed sequence of events among multiple processors on the network. • DF1 radio modem channel 0 driver This driver implements a protocol, optimized for use with radio modem networks, that is a hybrid between DF1 Full-duplex protocol and DF1 Half-duplex protocol, and therefore is not compatible with either of these protocols.
SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History OS302, Series C, FRN 7 OS401, Series C, FRN 7 OS501, Series C, FRN 7 released: November 2003 A-15 Enhancements • SLC 5/03 channel-to-channel passthru including the following operations: – Channel 0 DF1 Local to Channel 1 DH-485 Remote – Channel 0 DF1 Local to Channel 1 DH-485 Local – Channel 0 DH-485 Remote to Channel 1 DH-485 Remote – Channel 1 DH-485 Remote to Channel 0 DH-485 Remote • DF1 radio modem driver Additions of Store and
A-16 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History OS302, Series C, FRN 8 OS401, Series C, FRN 8 OS501, Series C, FRN 8 released: May 2004 Enhancements OS501, Series C, FRN 9 released: November 2004 Enhancements None IMPORTANT Only SLC 5/05 Series C processor hardware can support 100 Mbps Ethernet and increased Ethernet connections.
SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History A-17 Using RSLogix 500 V6.30 and higher, you can disable the SLC 5/05 SNMP functionality from within the Channel 1 Configuration by unchecking the SNMP Server Enable check box shown in Figure A.1. The default (checked SNMP Server Enable box shown in Figure A.1) allows you to connect to the SLC 5/05 using an SNMP client.
A-18 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History network as the SLC 5/05 using the RSLinx Ethernet/IP driver (AB_ETHIP-x), the RSLinx CIP Options need to be configured for Messaging as shown in Figure A.3. Figure A.3 RSLinx CIP Options Configuration In addition to reducing the number of RSLinx Messaging Connections per PLC to one, it is also recommended that the Messaging Connection Retry Interval be increased from the default of 1.
SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History OS302, Series C, FRN 10 OS401, Series C, FRN 10 OS501, Series C, FRN 10 released: January 2006 A-19 Enhancements • Three new explicit message instructions: – CEM (ControlNet Explicit Message) – DEM (DeviceNet Explicit Message) – EEM (EtherNet/IP Explicit Message) – SLC 5/05 only The CEM, DEM and EEM explicit message instructions allow generic Common Industrial Protocol (CIP) commands to be initiated to devices, such as drives, commu
A-20 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History DHCP is another option for dynamically configuring the IP address of the SLC 5/05 processor channel 1 Ethernet port (in addition to BOOTP). When the SLC 5/05 is configured for DHCP, it will broadcast a DHCP request at every power-up requesting that an IP address be assigned to it. Any DHCP server that receives the request can respond to it.
SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History OS302, Series C, FRN 11 OS401, Series C, FRN 11 OS501, Series C, FRN 11 released: June 2008 A-21 Enhancements • Modbus RTU Master capability on RS232 Channel 0 Modbus RTU Master capability is added to RS232 Channel 0 communication.
A-22 SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History Notes: Publication 1747-RM001G-EN-P - November 2008
Appendix B SLC Status File This appendix lists the: • SLC processor status file overview • status file detailed word/bit descriptions This appendix discusses the status file functions of the Fixed, SLC 500, SLC 5/01, SLC 5/02, SLC 5/03, SLC 5/04 and SLC 5/05 processors. The processors function similarly, but the higher numbered processors utilize more features. The tables in this appendix indicate which functions are supported by each processor.
B-2 SLC Status File The status file contains the following words: Table B.
SLC Status File B-3 Table B.
B-4 SLC Status File Table B.
SLC Status File B-5 Table B.2 Status File Functions Address Classification S:0 Description Fixed 5/01 5/02 5/03 5/04 5/05 Arithmetic and Scan Status Bits • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • The arithmetic flags are assessed by the processor following the execution of any math, logical, or move instruction.
B-6 SLC Status File Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/01 5/02 5/03 5/04 5/05 S:0/3 Status Sign Bit • • • • • • • • • • • • This bit is set by the processor when the result of a math, logical, or move instruction is negative. Otherwise the bit remains cleared. When a STI, I/O Slot, or Fault Routine interrupts normal execution of your program, the original value of S:0/3 is restored when execution resumes.
SLC Status File B-7 Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/01 5/02 5/03 5/04 5/05 S:1/6 Status Forces Installed Bit • • • • • • • • • • • • • • • • • • • This bit is set by the processor if you have installed forces in a ladder program. The forces may or may not be enabled. Otherwise the bit remains cleared. The processor Forced I/O LED flashes when forces are installed, but not enabled.
B-8 SLC Status File Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/01 5/02 5/03 5/04 5/05 S:1/10 Static Config Load Memory Module on Memory Error Bit • • • • • (See table on page B-60 for all setting combinations.) You can use this bit to transfer a memory module program to the processor in the event that a processor memory error is detected at power-up.
SLC Status File B-9 Table B.2 Status File Functions (Continued) Address Classification Description S:1/11 Static Config Load Memory Always Bit (See table on page B-60 for all setting combinations.) When this bit is set, you can overwrite a processor program with a memory module program by cycling processor power. A programming device is not required.
B-10 SLC Status File Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/01 S:1/12 Static Config Load Memory Module and Run Bit (See table on page B-60 for all setting combinations.) With this bit, you can overwrite a processor program with a memory module program by cycling processor power. A programming device is not required.
SLC Status File B-11 Table B.2 Status File Functions (Continued) Address S:1/12 Classification TIP continued Description Fixed 5/01 All modes in the fixed, SLC 5/01, and SLC 5/02 processors are considered to be remote because they do not have a keyswitch. 5/02 5/03 5/04 5/05 • • • • • • • The memory module you install in the processor must have a status file bit S:1/12 set. Loading takes place if the master password and/or password in the processor and memory module match.
B-12 SLC Status File Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/01 5/02 5/03 5/04 5/05 S:1/13 Dynamic Config Major Error Halted Bit • • • • • • • • • • • • • • • • This bit is set by the processor any time a major error is encountered. The processor enters a fault condition. Word S:6, Fault Code will contain a code which can be used to diagnose the fault condition.
SLC Status File B-13 Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/01 5/02 5/03 5/04 5/05 S:1/14 Status Access Denied Bit (OEM Lock) • • • • • • • • • • This bit is set during execution of the startup protection fault routine. Refer to S:1/9 for more information. • • • • STI (Selectable Timed Interrupt) Pending Bit • • • • • • • You can allow or deny future access to a processor file. Set this bit to deny access.
B-14 SLC Status File Table B.2 Status File Functions (Continued) Address Classification Description S:2/1 Static Config STI (Selectable Timed Interrupt) Enabled Bit Fixed 5/01 5/02 5/03 5/04 5/05 • • • • • • • • • • • • • • • • • • • • • This bit is set in its default condition, or when set by the STE or STS instruction. If set, it allows execution of the STI if the STI file (S:31) and STI setpoint (S:30) are non-zero.
SLC Status File B-15 Table B.2 Status File Functions (Continued) Address Classification Description S:2/5 Status Incoming Command Pending Bit (Channel 1) Fixed 5/01 5/02 5/03 5/04 5/05 • • • • • • • • • • • • • • • • This bit is set when the processor determines that another node on the network has requested information or supplied a command to it. This bit can be set at any time. This bit is cleared when the processor services the request (or command).
B-16 SLC Status File Table B.2 Status File Functions (Continued) Address Classification Description S:2/9 Static Config Memory Module Program Compare Fixed 5/01 5/02 5/03 5/04 5/05 • • • • • • • • • • • • • • • When this bit is set inside a valid program that is contained in a memory module, no modification of the NVRAM user program files is allowed. This includes online editing, program downloading, and clear memory commands.
SLC Status File B-17 Table B.2 Status File Functions (Continued) Address Classification Description S:2/14 Dynamic Config Math Overflow Selection Bit Fixed 5/01 5/02 5/03 5/04 5/05 • • • • Set this bit when you intend to use 32-bit addition and subtraction.
B-18 SLC Status File Table B.2 Status File Functions (Continued) Address Classification Description S:2/15 Dynamic Config Communications Servicing Selection Bit (Ethernet Channel 1 for SLC 5/05) (DH+ Channel 1 for SLC 5/04) (DH-485 Channel 1 for SLC 5/03) When set, only one communication request/command can be serviced per END, TND, REF, or SVC. When clear, all serviceable incoming or outgoing communication requests/commands can be serviced per END, TND, REF, or SVC.
SLC Status File B-19 Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/01 5/02 S:3L Status Current/Last 10 ms Scan Time • • 5/03 5/04 5/05 • • • The value of this byte tells you how much time elapses in a program cycle. A program cycle includes: • scanning the ladder program, • housekeeping, • scanning the I/O, and • servicing of the communication port.
B-20 SLC Status File Table B.2 Status File Functions (Continued) Address Classification S:3L continued Description Fixed 5/01 5/02 5/03 5/04 5/05 • • • • • Application example: Your application requires that each and every program scan execute in the same length of time. You measure the maximum and minimum scan times and find them to be 40 ms and 20 ms. You can make every scan equal to precisely 50 ms by programming the following rungs as the last rungs of your program.
SLC Status File B-21 Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/01 S:4 Status Free Running Clock • 5/02 5/03 5/04 5/05 • • • • • • • • Only the first 8 bits (byte value) of this word are assessed by the processor. This value is zeroed at powerup in the REM Run mode. You can use any individual bit of this byte in your user program as a 50% duty cycle clock bit. Clock rates for S:4/0 to S:4/7 are: 20, 40, 80, 160, 320, 640, 1280, and 2560 ms.
B-22 SLC Status File Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/01 5/02 5/03 5/04 5/05 S:5/0 Dynamic Config Overflow Trap Bit • • • • • When this bit is set by the processor, it indicates that a mathematical overflow has occurred in the ladder program. See S:0/1 for more information. If this bit is ever set upon execution of the END, TND, or REF instruction, major error (0020) will be declared.
SLC Status File B-23 Table B.2 Status File Functions (Continued) Address Classification Description S:5/4 Dynamic Config M0-M1 Referenced on Disabled Slot Bit Fixed 5/01 5/02 5/03 5/04 5/05 • • • • • • • • • • • • • • • • • • • • • • • This bit is set whenever any instruction references an M0 or M1 module file element for a slot that is disabled (via its I/O slot enable bit).
B-24 SLC Status File Table B.2 Status File Functions (Continued) Address Classification Description S:5/11 Status Battery Low Bit Fixed 5/01 5/02 5/03 5/04 5/05 • • • • • • • • • • • • • This bit is set whenever the Battery Low LED is on. The bit is cleared when the Battery Low LED is off.
SLC Status File B-25 Table B.2 Status File Functions (Continued) Address Classification Description S:5/15 Status ASCII String Manipulation Error Fixed 5/01 5/02 5/03 5/04 5/05 • • • This bit applies to SLC 5/03 (OS301 and higher), SLC 5/04, and SLC 5/05 processors. This bit is set to 1 when an attempt is made to process a string using an ASCII instruction that exceeds 82 characters in length.
B-26 SLC Status File Table B.2 Status File Functions (Continued) Address Classification Description Fixed 5/01 5/02 5/03 5/04 5/05 S:6 Status Major Error Fault Code • • • • • • • • • • • • • A hexadecimal code is entered in this word by the processor when a major error is declared. Refer to S:1/13. The code defines the type of fault, as indicated on the following pages. This word is not cleared by the processor.
SLC Status File B-27 Table B.3 S:6 Error Codes Address S:6 continued Error Code (Hex) Errors Fault Classification NonUser Processor User NonRecov Recov Fixed 5/01 5/02 5/03 5/04 5/05 0001 NVRAM error. X • • • • • 0002 Unexpected hardware watchdog timeout. X • • • • • 0003 Memory module memory error. This error can also occur while going into the REM Run mode. X • • • • 0004 Memory error occurred while in the Run X mode.
B-28 SLC Status File Table B.3 S:6 Error Codes (Continued) Address S:6 continued Error Code (Hex) Errors Fault Classification NonUser 0020 A minor error bit is set at the end of the scan. Refer to S:5 minor error bits. 0021 Remote power failure of an expansion I/O chassis occurred.
SLC Status File B-29 Table B.3 S:6 Error Codes (Continued) Address S:6 continued Error Code (Hex) Errors Fault Classification NonUser Processor User NonRecov Recov Fixed 5/01 5/02 5/03 5/04 5/05 002B Either the file number exists, but it is not the correct file type, or the file number does not exist. X • • • 002C The indirectly referenced element does not exist, but the file type is correct and it exists. For example, T4:[N7:0] N7:0=10, but T4 only goes to T4:9.
B-30 SLC Status File Slot xx Slot xx Slot xx Slot xx 8 9 10 11 12 13 14 15 08 09 0A 0B 0C 0D 0E 0F 16 17 18 19 20 21 22 23 10 11 12 13 14 15 16 17 24 25 26 27 28 29 30 18 19 1A 1B 1C 1D 1E 1F (2) 0 1 2 3(1) 4 5 6 7 Publication 1747-RM001G-EN-P - November 2008 00 01 02 03 04 05 06 07 (3) (1) This value indicates that the slot was not found (500 fixed controller).
SLC Status File B-31 Table B.3 S:6 Error Codes Address S:6 continued Error Code (Hex) User Program Instruction Errors Fault Classification NonUser Processor User NonRecov Recov Fixed 5/01 5/02 5/03 5/04 5/05 0030 Attempt was made to jump to one too many nested subroutine files. This code can also mean that a program has potentially recursive routines. X • • • • • 0031 An unsupported instruction reference was detected.
B-32 SLC Status File Table B.3 S:6 Error Codes (Continued) Address S:6 continued Error Code (Hex) User Program Instruction Errors Fault Classification NonUser Processor User NonRecov Recov 5/02 5/03 5/04 5/05 • • • • • xx51 A “stuck” runtime error is detected on an I/O module. (xx = slot number) xx52 A module required for the user program is detected as missing or removed.
SLC Status File B-33 Table B.3 S:6 Error Codes (Continued) Address S:6 continued Error Code (Hex) User Program Instruction Errors Fault Classification NonUser Processor User NonRecov Recov X Fixed 5/01 5/02 5/03 5/04 5/05 • • • • xx5A Hardware interrupt problem. (xx = slot number) xx5B G file configuration error - user program G file size exceeds capacity of the module.
B-34 SLC Status File Table B.3 S:6 Error Codes (Continued) Address S:6 continued Error Code (Hex) User Program Instruction Errors Fault Classification NonUser Processor User NonRecov Recov Fixed 5/01 5/02 5/03 5/04 5/05 • • • xx80 to xx8F Identifies a specialty I/O module X specific major error. Refer to the user manual supplied with the specialty module. (xx = slot number) xx90 Interrupt problem on disabled slot. X • • • • xx91 A disabled slot has faulted.
SLC Status File B-35 Table B.4 Status File Functions Address Classification Description Fixed 5/01 5/02 5/03 5/04 5/05 S:7 and S:8 Status Suspend Code/Suspend File • • • • • When a non-zero value appears in S:7, it indicates that the SUS instruction identified by this value has been evaluated as true, and the Suspend Idle mode is in effect. This pinpoints the conditions in the application that caused the Suspend Idle mode. This value is not cleared by the processor.
B-36 SLC Status File Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/01 5/02 5/03 5/04 5/05 S:11 and S:12 Dynamic Config I/O Slot Enables • • • • • • • • • • • • These two words are bit mapped to represent the 30 possible I/O slots in an SLC 500 system. S:11/0 represents I/O slot 0 for fixed I/O systems. (Slot 0 is used for the CPU in modular systems.) S:11/1 through S:12/14 represent I/O slots 1-30. S:12/15 is unused.
SLC Status File B-37 Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/01 5/02 5/03 5/04 5/05 S:13 and S:14 Status and Dynamic Config Math Register • • • • • • • • • • • • Use this double register to produce 32-bit signed divide and multiply operations, precision divide or double divide operations, and 5-digit BCD conversions. These two words are used in conjunction with the MUL, DIV, DDV, FRD, and TOD math instructions.
B-38 SLC Status File Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/01 5/02 5/03 5/04 S:15L Static Config Node Address • • • • This byte value contains the node address of your processor on the DH-485 or DH+ link. Each device on the DH-485 link must have a unique address between the decimal values 0 and 31. Each device on the DH+ link must have a unique address between the decimal values 0 and 63.
SLC Status File B-39 Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/01 S:15H Static Config When a configure channel command is received for channel 1, the node address is overwritten with the value contained in your channel configuration. Baud Rate This byte value contains a code used to select the baud rate of the processor on the DH-485 or DH+ link. SLC 5/01 and fixed processors provide a baud rate of 19.2K or 9.6K only.
B-40 SLC Status File Table B.4 Status File Functions (Continued) Address Classification Description S:16 and S:17 Status Test Single Step - Start Step On - Rung/File Fixed 5/01 5/02 5/03 5/04 5/05 • • • • • • • • • • • • • These registers indicate the executable rung (word S:16) and file (word S:17) number that the processor executes next when operating in the Test Single Step mode.
SLC Status File B-41 Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/01 S:20 and S:21 Status Test - Fault/Powerdown - Rung/File 5/02 5/03 5/04 5/05 • • • • • • • These registers indicate the executable rung (word S:20) and file (word S:21) number that the processor last executed before a major error or powerdown occurred. To enable this feature, you must select the Test Single Step option at the time you save your program.
B-42 SLC Status File Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/01 S:22 Status Maximum Observed Scan Time 5/02 5/03 5/04 5/05 • • • • • • • • • • • • • This word indicates the maximum observed interval between consecutive scans. Consecutive scans are defined as intervals between file 2/rung 0 and the END, TND, or the REF instruction. This value indicates, in 10 ms increments, the time elapsed in the longest program cycle of the processor.
SLC Status File B-43 Table B.4 Status File Functions (Continued) Address Classification Description S:24 Dynamic Config Index Register Fixed 5/01 5/02 5/03 5/04 5/05 • • • • • • • • • • • • • This word indicates the element offset used in indexed addressing. When an STI, I/O Slot, or Fault Routine interrupts normal execution of your program, the original value of this register is restored when execution resumes.
B-44 SLC Status File Table B.4 Status File Functions (Continued) Address Classification Description S:27 and S:28 Status I/O Interrupt Enabled Fixed 5/01 5/02 5/03 5/04 5/05 • • • • • • • • • • These two words are bit-mapped to the 30 I/O slots. Bits S:27/1 through S:28/14 refer to slots 1 through 30. Bits S:27/0 and S:28/15 are reserved. The default value of each bit is 1 (set).
SLC Status File B-45 Table B.4 Status File Functions (Continued) Address Classification Description S:30 Dynamic Config Selectable Timed Interrupt - Setpoint Fixed 5/01 5/02 5/03 5/04 5/05 • • • • • • • • • • You enter the timebase, in tens of milliseconds, to be used in the selectable timed interrupt. Your STI routine executes per the value you enter. Write a zero value to disable the STI.
B-46 SLC Status File Table B.4 Status File Functions (Continued) Address Classification Description S:32 Status I/O Interrupt Executing Fixed 5/01 5/02 5/03 5/04 5/05 • • • • You can interrogate this word inside your DII subroutine if you wish to know if these higher priority interrupts have interrupted an executing ISR. You may also use this value to discern interrupt slot identity when multiplexing two or more specialty I/O module interrupts to the same ISR.
SLC Status File B-47 Table B.4 Status File Functions (Continued) Address Classification Description S:33/3 Status Selection Status (Channel 0) Fixed 5/01 5/02 5/03 5/04 5/05 • • • • • • • • • • • • When set, this bit indicates that the channel 0 communication port is in the System mode (DF1 mode). When reset, this bit indicates that channel 0 is in the User mode (ASCII mode). Use your programming devices channel configuration utility to change this selection.
B-48 SLC Status File Table B.4 Status File Functions (Continued) Address Classification Description S:33/7 Dynamic Config Message Servicing Selection (Channel 1) Fixed 5/01 5/02 5/03 5/04 5/05 • • • • • • • • • This bit is only valid when the channel 1 Comms Servicing Selection bit (S:2/15) is clear (which selects service all commands). When S:33/7 is clear and S:2/15 is clear, all outgoing channel 1 MSG instructions are serviced per END, TND, SVC, or REF instruction.
SLC Status File B-49 Table B.4 Status File Functions (Continued) Address Classification Description Fixed 5/01 S:33/10 Dynamic Config Discrete Input Interrupt Reconfiguration Bit 5/02 5/03 5/04 5/05 • • • • • • Set this bit with your user program or programming terminal to cause the DII function to reconfigure itself at the next interrupt occurrence or end of each scan (END, TND, or REF). This bit is applied upon a DII ISR, fault routine, STI ISR, or Event ISR exit.
B-50 SLC Status File Table B.4 Status File Functions (Continued) Address Classification Description S:33/13 Static Config Scan Time Timebase Selection Fixed 5/01 5/02 5/03 5/04 5/05 • • • • • • • • • This bit determines the timebase used to average the Scan time (S:23) and the maximum Scan Time (S:22). When clear, the value contained in the average and maximum scan times represent the number of 10 ms increments that have occurred.
SLC Status File B-51 Table B.4 Status File Functions (Continued) Address Classification Description S:34/0 Dynamic Config DH-485 Passthru Disabled Bit Fixed 5/01 5/02 5/03 5/04 5/05 • • • When channel 0 is configured for DH-485 protocol, this bit provides the capability to pass received packets between channels. When set, the processor does not support passthru. When reset, the processor allows packets to be passed from one channel to the other.
B-52 SLC Status File Table B.4 Status File Functions (Continued) Address Classification Description S:34/5 Dynamic Config DF1 Passthru Enabled Bit Fixed 5/01 5/02 5/03 5/04 5/05 • • • • • • • • • • • • If channel 0 is enabled with a DF1 protocol and this bit is SET, then the passthru operation is enabled between Channel 0 and Channel 1. Passthru supported DF1 protocols include DF1 Full-duplex, DF1 Half-duplex, and DF1 Radio Modem.
SLC Status File B-53 Table B.4 Status File Functions (Continued) Address Classification Description S:36/8 Status DII Lost Fixed 5/01 5/02 5/03 5/04 5/05 • • • • • • • • • This bit is set anytime a DII interrupt occurs while the DII Pending bit (S:2/11) is also set. When set, you are notified that a DII interrupt has been lost. For example, the interrupt is lost because a previous interrupt was already pending and waiting execution.
B-54 SLC Status File Table B.4 Status File Functions (Continued) Address Classification Description S:39 Dynamic Config Clock/Calendar Day Fixed 5/01 5/02 5/03 5/04 5/05 • • • • • • • • • • • • • • • This value contains the day value of the clock/calendar. Valid range is 1 to 31. To disable the clock/calendar, write zeros to all clock or calendar words (S:37 to S:42). The first day of the month equals the value of 1. See status word S:53 for Day-of-Week.
SLC Status File B-55 Table B.4 Status File Functions (Continued) Address Classification Description S:46 Dynamic Config Discrete Input Interrupt - File Number Fixed 5/01 5/02 5/03 5/04 5/05 • • • • • • • • • You enter a program file number (3-255) to be used as the discrete input interrupt subroutine. Write a zero value to disable the function. This value is applied upon detection of a DII Reconfigure bit, each DII ISR exit, and each end of scan (END, TND, or REF).
B-56 SLC Status File Table B.4 Status File Functions (Continued) Address Classification Description S:49 Dynamic Config Discrete Input Interrupt - Compare Value Fixed 5/01 5/02 5/03 5/04 5/05 • • • • • • • • • • • • You enter a bit mapped value that corresponds to the bit transitions that must occur in the discrete I/O card for a count or interrupt to occur. Only bits 0 to 7 are used in the DII function.
SLC Status File B-57 Table B.4 Status File Functions (Continued) Address Classification Description S:53L Dynamic Config Day-of-Week Fixed 5/01 5/02 5/03 5/04 5/05 • • • This value contains the day-of-week value of the clock/calendar. Valid range is 0 to 6 (Sunday=0). To disable the clock/calendar, write zeros to all clock and calendar words (S:37 to S:42).
B-58 SLC Status File Table B.4 Status File Functions (Continued) Address Classification Description S:61 Status Processor Series Fixed 5/01 5/02 5/03 5/04 5/05 • • • • • • • • • • • • • • • • • • Indicates the processor series. For example, the value of 0 indicates series A and the value of 1 indicates series B. S:62 Status Processor Revision Indicates the processor revision. For example, the value of 1 indicates REV1 and the value of 2 indicates REV2.
SLC Status File B-59 Table B.4 Status File Functions (Continued) Address Classification Description S:67 to S:82 Dynamic Config DF1 Radio Modem Store and Forward Table Fixed 5/01 5/02 5/03 5/04 5/05 • • • In DF1 Radio Modem with Store and Forward enabled in the channel configuration, these 16 words are bit mapped to represent the 255 possible nodes and the broadcast address. The user is required to set these bits to enable Store and Forward operation.
B-60 SLC Status File The following table lists all combination settings for S:1/10, S:1/11 and S:1/12. Table B.
Appendix C Memory Usage This appendix provides: • instruction words for the Fixed, SLC 5/01, SLC 5/02, SLC 5/03, SLC 5/04, and SLC 5/05 processor. • examples on how to estimate the total memory usage of your system. Memory Usage Overview If you want to use a See page Fixed or SLC 5/01 processor C-2 SLC 5/02 processor C-7 SLC 5/03 processor C-13 SLC 5/04 or SLC 5/05 processor C-13 SLC 500 controllers have the following user memory capacities. Table C.
C-2 Memory Usage The number of words used by an instruction is indicated in the following table. Since the program is compiled by the programmer, it is only possible to establish estimates for the instruction words used by individual instructions. The calculated memory usage will normally be greater than the actual memory usage, due to compiler optimization. Fixed and SLC 5/01 Processors Table C.
Memory Usage C-3 Table C.2 SLC 500 Fixed and SLC 5/01 List of Instructions (Continued) Mnemonic Memory Usage (user words) Name Instruction Type Page NEG 1.50 Negate Data Handling 5-24 NEQ 1.50 Not Equal Comparison 3-2 NOT 1.00 Not Data Handling 5-23 OR 1.50 Or Data Handling 5-21 OSR 1.00 One-shot Rising Basic 2-5 OTE 0.75 Output Energize Basic 2-4 OTL 0.75 Output Latch Basic 2-4 OTU 0.75 Output Unlatch Basic 2-4 RES 1.00 Reset Basic 2-20 RET 0.
C-4 Memory Usage Estimating Total Memory Usage of Your System Using a Fixed or SLC 5/01 Processor __________ 1. Calculate the total instruction words used by the instructions in your program and enter the result. Refer to the table on page C-2. __________ 2. Multiply the total number of rungs by 0.375 and enter the result. __________ 3. Multiply the total number of data words (excluding the status field and I/O data words) by 0.25 and enter the result. __________ 4.
Memory Usage C-5 Fixed Controller Memory Usage Example L20B Fixed I/O Controller 42 XIC and XIO 42 x 1.00 = 42.00 10 OTE instructions 10 x 0.75 = 7.50 10 TON instructions 10 x 1.00 = 10.00 1 CTU instruction 1 x 1.00 = 1.00 1 RES instruction 1 x 1.00 = 1.00 Instruction Usage 61.50 21 rungs 21 x 0.375 = 7.87 37 data words 37 x 0.250 = 9.25 User Program Total 78.62 2 I/O data words 2 x 0.75 = 1.50 1 slot 1 x 0.75 = 0.75 Overhead 65.
C-6 Memory Usage SLC 5/01 Processor Memory Usage Example 1747-L514 processor, 30-slot configuration, (15) 1746-IA16, (10) 1746-OA8, (1) 1747-DCM full configuration, (1) 1746-NI4, (1) 1746-NIO4I 50 XIC and XIO 50 x 1.00 = 50.00 15 OTE instructions 15 x 0.75 = 11.25 5 TON instructions 5 x 1.00 = 5.00 3 GRT instructions 3 x 1.50 = 4.50 1 SCL instruction 1 x 1.75 = 1.75 1 TOD instruction 1 x 1.00 = 1.00 3 MOV instructions 3 x 1.50 = 4.50 10 CTU instructions 10 x 1.00 = 10.
Memory Usage C-7 The number of instruction words used by an instruction is indicated in the following table. Since the program is compiled by the programmer, it is only possible to establish estimates for the instruction words used by individual instructions. The calculated memory usage will normally be greater than the actual memory usage, due to compiler optimization. SLC 5/02 Processor Table C.3 SLC 5/02 List of Instructions Mnemonic Memory Usage (user words) Name Instruction Type Page ADD 1.
C-8 Memory Usage Table C.3 SLC 5/02 List of Instructions (Continued) Mnemonic Memory Usage (user words) Name Instruction Type Page LIM 1.50 Limit Test Comparison 3-5 LFL 1.50 LIFO Load Data Handling 5-28 LFU 1.50 LIFO Unload Data Handling 5-28 MCR 0.50 Master Control Reset Program Flow Control 6-6 MEQ(1) 1.50 Masked Comparison for Equal Comparison 3-4 MOV 1.50 Move Data Handling 5-17 MSG 34.75 Message Communication 12-5 MUL 1.50 Multiply Math 4-8 MVM 1.
Memory Usage C-9 Table C.3 SLC 5/02 List of Instructions (Continued) Mnemonic Memory Usage (user words) Name Instruction Type Page TND 0.50 Temporary End Program Flow Control 6-7 TOD 1.00 Convert to BCD Data Handling 5-2 TOF 1.00 Timer Off-delay Basic 2-10 TON 1.00 Timer On-delay Basic 2-9 XIC(1) 1.00 Examine If Closed Basic 2-3 XIO(1) 1.00 Examine If Open Basic 2-3 XOR 1.
C-10 Memory Usage Estimating Total Memory Usage of Your System Using a SLC 5/02 Processor __________ 1. Calculate the total instruction words used by the instructions in your program and enter the result. Refer to the table on page -7. __________ 2. Multiply the total number of rungs by 0.375 and enter the result. __________ 3. If you are using a 1747-L524 and have enabled the Single Step Test mode, multiply the total number of rung by 0.375 and enter the result. __________ 4.
Memory Usage C-11 SLC 5/02 Memory Usage Example 1747-L524 series C processor, 30-slot configuration, (15) 1746-IA16, (10) 1746-OA8, (1) 1747-DCM full configuration, (1) 1746-NI4, (1) 1746-NIO4I 50 XIC and XIO 50 x 1.00 = 50.00 15 OTE instructions 15 x 0.75 = 11.25 5 TON instructions 5 x 1.00 = 5.00 3 GRT instructions 3 x 1.50 = 4.50 1 SCL instruction 1 x 1.75 = 1.75 1 TOD instruction 1 x 1.00 = 1.00 3 MOV instructions 3 x 1.50 = 4.50 10 CTU instructions 10 x 1.
C-12 Memory Usage User Word Comparison Between SLC 5/03 (and higher) Processors and the SLC 5/02 Processor The SLC 5/03 (and higher) processors and the SLC 5/02 processor accumulate user words differently during the creation of a user program. The SLC 5/02 processor is generally more efficient in its word usage than the SLC 5/03 (and higher) processors. However, the SLC 5/02 processor word usage is difficult to estimate since it is tied to the architecture of the microprocessor.
Memory Usage C-13 Data Words Files 0 and 1 In the SLC 5/02 processor, each I/O data word consumes 0.75 words of memory. In the SLC 5/03 processor, each I/O data word consumes 3 words of data. File 2 The status file word usage is contained in the overhead values for both the SLC 5/02 and SLC 5/03 processors. File 3 to 255 In the SLC 5/02 processor, 4 data words consume the same amount of memory as 1 instruction word.
C-14 Memory Usage Table C.5 SLC 5/03, SLC 5/04 and SLC 5/05 List of Instructions (Continued) Instruction Type Page OS302, OS401, OS501 Series C, FRN 10+ Name OS302, OS401, OS501 Series C Memory Usage (user words) OS302, OS401, OS501 Applies to SLC OS301, OS400 Mnemonic ACL • • • • 2.00 ASCII Clear Receive and/or Send Buffer ASCII 10-9 ACN • • • • 3.00 String Concatenate ASCII 10-11 • • • 2.00 Arc Cosine Math 4-29 • • • 3.00, 4.00 Add Math 4-5 • • • 4.
Memory Usage C-15 Table C.5 SLC 5/03, SLC 5/04 and SLC 5/05 List of Instructions (Continued) OS302, OS401, OS501 OS302, OS401, OS501 Series C OS302, OS401, OS501 Series C, FRN 10+ • • 2.00 Decode 4 to 1 of 16 Data Handling 5-10 • • • • 2.00 Double Divide Math 4-11 • • 6.00 Diagnostic Detect Application Specific 7-18 • • 2.00 Degree Data Handling 5-8 • 74.00 DeviceNet Explicit Message Communication 12-52 FP • DEM DIV • • FP • • • 3.00, 4.
C-16 Memory Usage Table C.5 SLC 5/03, SLC 5/04 and SLC 5/05 List of Instructions (Continued) LES • FP Page OS302, OS401, OS501 Series C, FRN 10+ LES Instruction Type OS302, OS401, OS501 Series C OS300 FP Name • • • • 3.00 Less Than or Equal Comparison 3-3 • • • • 3.00 Less Than Comparison 3-3 • • • • 3.00 Less Than Comparison 3-3 FP = floating point LEQ Memory Usage (user words) OS302, OS401, OS501 Applies to SLC OS301, OS400 Mnemonic LFL • • • • • 3.
Memory Usage C-17 Table C.5 SLC 5/03, SLC 5/04 and SLC 5/05 List of Instructions (Continued) Page 2-20 OS302, OS401, OS501 Series C, FRN 10+ Instruction Type OS302, OS401, OS501 Series C Name OS302, OS401, OS501 Memory Usage (user words) OS301, OS400 Applies to SLC OS300 Mnemonic RES • • • • • 1.00 Reset Basic RET • • • • • 1.00 Return from Subroutine Program Flow Control 6-3 RHC • • 2.00 Read High Speed Clock Application Specific 7-17 RMP • • 2.
C-18 Memory Usage Table C.5 SLC 5/03, SLC 5/04 and SLC 5/05 List of Instructions (Continued) Page OS302, OS401, OS501 Series C, FRN 10+ Instruction Type OS302, OS401, OS501 Series C Name OS302, OS401, OS501 Memory Usage (user words) OS301, OS400 Applies to SLC OS300 Mnemonic TOF • • • • • 1.00 Timer Off-delay Basic 2-10 TON • • • • • 1.00 Timer On-delay Basic 2-9 XIC • • • • • 1.00 Examine If Closed Basic 2-3 XIO • • • • • 1.
Memory Usage C-19 Estimating Total Memory Usage of Your System Using an SLC 5/03, SLC 5/04, or SLC 5/05 Processor __________ 1. Add the total number of data file words used (excluding the status file and I/O data words) and enter the result. __________ 2. Multiply the total number of I/O data words by 3 and enter the result. __________ 3. Multiply the total number of I/O slots, used or unused, by 3 and enter the result. __________ 4. To account for processor overhead, enter 236. __________ 5.
C-20 Memory Usage SLC 5/03, SLC 5/04, or SLC 5/05 Memory Usage Example 1747-L532 processor, 30-slot configuration, (15) 1746-IA16, (10) 1746-OA8, (1) 1747-DCM full configuration, (1) 1746-NI4, (1) 1746-NIO4I 100 data words 100 x 1.00 = 100.00 49 I/O data words 49 x 3.00 = 147.00 30 slot 30 x 3.00 = 90.00 Overhead 236.00 10 is the highest data table file number 10 x 5.00 = 50.00 4 is the highest program file number 4 x 5.00 = 20.00 Subtotal 643.
Appendix D Programming Instruction References This appendix lists all of the available programming instructions along with their parameters, valid addressing modes, and file types. Valid Addressing Modes and File Types The following addressing modes are available. Table D.1 Available Addressing Modes Addressing Mode Example Direct N7:0 Indexed Direct #N7:0 Indirect N7:[N10:3] Indexed Indirect #N7:[N10:3] The following file types are available. Table D.
D-2 Programming Instruction References Understanding the Different Addressing Modes The following descriptions will help you understand how to structure a specific type of address. Direct Addressing The data stored in the specified address is used in the instruction. For example: N7:0 ST20:5 T4:8.ACC Indexed Addressing You may specify an address as being indexed by placing the “#” character in front of the address.
Programming Instruction References D-3 #N7:[N10:3] where N10:3 = 20 and S:24 = 15 The actual address used by the instruction is N7:35. Table D.
D-4 Programming Instruction References Table D.
Programming Instruction References D-5 Table D.
D-6 Programming Instruction References Table D.
Programming Instruction References D-7 Table D.
D-8 Programming Instruction References Table D.
Programming Instruction References D-9 Table D.
D-10 Programming Instruction References Table D.
Programming Instruction References D-11 Table D.
D-12 Programming Instruction References Table D.
Programming Instruction References D-13 Table D.
D-14 Programming Instruction References Table D.
Programming Instruction References D-15 Table D.
D-16 Programming Instruction References Table D.
Programming Instruction References D-17 Table D.4 Available Addressing Modes (Continued) Instruction Description Instruction Parameter Valid Addressing Mode(s) Valid File Types Immediate Values SCP(2) Scale with Parameters input direct, indexed direct indirect, indexed indirect O, I, S, B, T, C, R, N, F, A, ST, M none input min. direct, indexed direct indirect, indexed indirect O, I, S, B, T, C, R, N, F, A, ST, M -32,768 to 32,767 f-min to f-max input max.
D-18 Programming Instruction References Table D.
Programming Instruction References D-19 Table D.
D-20 Programming Instruction References Table D.
Programming Instruction References D-21 Message lengths for SLC 5/05 processors are shown in the next table. TIP Message lengths are based on Ethernet buffer size of 2108 bytes (includes command header and system addressing in addition to actual file data). The local file is the destination file for reads and the source files for writes.
D-22 Programming Instruction References Notes: Publication 1747-RM001G-EN-P - November 2008
Appendix E Data File Organization and Addressing This chapter discusses the following topics.
E-2 Data File Organization and Addressing hard to disk, replacing the original disk version with the edited version. The hard disk is the recommended location for a processor file. PROGRAMMING DEVICE Hard Disk Workspace 01 01 02 03 04 Uniquely named processor files Processor files are created in the offline mode using the programming device. These files are then restored (downloaded), to the processor for online operation.
Data File Organization and Addressing E-3 • Status (file 2) - This file stores controller operation information. This file is useful for troubleshooting controller and program operation. • Bit (file 3) - This file is used for internal relay logic storage. • Timer (file 4) - This file stores the timer accumulator and preset values and status bits. • Counter (file 5) - This file stores the counter accumulator and preset values and the status bits.
E-4 Data File Organization and Addressing Table E.
Data File Organization and Addressing E-5 Specifying Logical Addresses You assign logical addresses to instructions from the highest level (element) to the lowest level (bit). Addressing examples are shown in the table below. To specify the address of a Use these parameters(1) Word within an integer file N 7 : 2 File Type File Number File Delimiter Word Number Word within a structure file (for example, a timer file) T 4 : 7 .
E-6 Data File Organization and Addressing To specify the address of a Use these parameters(1) Bit within a bit file B 3 / 31 File Type File Number Bit Delimiter Bit Number R 6 : Bit within an integer file 7 / DN File Type File Number File Delimiter Structure Number Delimiter Mnemonic (1) Some programming devices support short addressing. This allows you to eliminate the file number and file delimiter from addresses.
Data File Organization and Addressing Slot Inputs Outputs 0 1 2 24 6 None 16 6 8 E-7 Table E.2 Data File 0 - Output Image 15 14 13 12 11 10 09 08 07 06 05 Slot 0 Outputs (0 to 15) Slot 1 Outputs (0 to 5) 04 03 02 01 00 x O:0 INVALID O:1 Slot 2 Outputs (0 to 7) x O:2 Table E.3 Data File 1 - Input Image 15 14 Slot 0 Inputs (0 to 15) x Slot 0 Inputs (16 to 23) INVALID Slot 1 Inputs (0 to 5) INVALID 13 12 11 10 09 08 07 06 05 04 x x 03 02 01 00 I:0 I:0.
E-8 Data File Organization and Addressing Assign I/O addresses to fixed I/O controllers Table E.4 Addressing Format Format Explanation O Output I Input : Element delimiter Slot number Fixed I/O controller: 0 (decimal) e Left slot of expansion chassis: 1 Right slot of expansion chassis: 2 O:e.s/b I:e.s/b . Word delimiter. Required only if a word number is necessary as noted below.
Data File Organization and Addressing E-9 Slots 1 through 10 contain I/O modules. The remaining slots are saved for future I/O expansion. The figure indicates the number of inputs and outputs in each slot and also shows how these inputs and outputs are arranged in the data files. For these files, the element size is always 1 word.
E-10 Data File Organization and Addressing Specifying Indexed Addresses The indexed address symbol is the # character. Place the # character immediately before the file-type identifier in a logical address. You can use more than one indexed address in your ladder program. Enter the offset value in word 24 of the status file (S:24). All indexed instructions use the same word S:24 to store the offset value. The processor starts operation at the base address plus the offset.
Data File Organization and Addressing E-11 In this example, the processor uses the following addresses: Table E.5 Addresses used for Indexing Value: Base Address: Offset Value in S:24 Offset Address: Source N7:10 10 N7:20 Destination N7:50 10 N7:60 SLC 5/03 (OS301 and higher), SLC 5/04, and SLC 5/05 processors: If the indexed address is a floating point (F8:) data file, then the index offset value in S:24 is the offset in elements.
E-12 Data File Organization and Addressing SLC 5/03 (OS301 and higher) SLC 5/04, and SLC 5/05 processors: When an indexed string data file is specified, indexed addressing is not allowed to cross a string element boundary. A run-time error will occur if you use an offset value that results in crossing a string element boundary. TIP If a file is constant protected, indexing across file boundaries is not allowed. Example The figure below indicates the maximum offset for word address #T4:3.
Data File Organization and Addressing E-13 Monitoring Indexed Addresses The offset address value is not displayed when you monitor an indexed address. For example, the value at N7:2 appears when you monitor indexed address #N7:2. Example If your application requires you to monitor indexed data, we recommend that you use a MOV instruction to store the value. N10:2 will contain the data value that was added to T4:0.ACC. File Instructions The # symbol is also required for addresses in file instructions.
E-14 Data File Organization and Addressing Effects of Program Interrupts on Index Register S:24 When normal program operation is interrupted by the user error handler, an STI, or an I/O interrupt, the content of index register S:24 is saved; then, when normal program operation is resumed, the content of index register S:24 is restored.
Data File Organization and Addressing E-15 Examples Table E.6 Valid Addresses Valid Address Variable Explanation N7:[C5:7.ACC] Word number The word number is the accumulated value of counter 7 in file 5. B3/[I:0.17] Bit number The bit number is stored in input word 17. N[N7:0]:[N9:1] File and word number The file number is stored in integer address N7:0 and the word number in integer address N9:1. St10:[N7:0].1 Element number The element number is stored in N7:0. I:[N7:0].
E-16 Data File Organization and Addressing ATTENTION If you are using file instructions and also indexed addressing, make sure that you monitor and/or load the correct offset value prior to using an indexed address. Otherwise, unpredictable operation could occur, resulting in possible personal injury and/or damage to equipment. The following paragraphs explain user-created files as they apply to Bit Shift instructions, Sequencer instructions, Copy File, and Fill File instructions.
Data File Organization and Addressing E-17 Sequencer Instructions The following figure shows a user-defined file within bit data file 3. For this particular user-defined file, you would enter the following parameters when programming the instruction. Bit Data File 3 15 0 0 1 2 3 4 5 6 7 #B3:4 8 9 10 11 0 1 2 3 4 5 6 Address of the user-defined file is #B3:4. Length of the file is 6 elements beyond the starting address (elements labeled 0-6 in the diagram). • #B3:4 - The address of the file.
E-18 Data File Organization and Addressing The following figure shows a user-defined file within Data File 0- Output Image. We used this particular data file configuration in regard to I/O addressing on page B-12. Here, we are defining a file 5 elements long. Note that for the output file (and the input file as well), an element is always one word, referenced as the slot and word taken together. For example, element O:3.0 refers to output file, slot 3, word 0.
Data File Organization and Addressing E-19 When entering values into an instruction or data table element, you can specify the radix of your entry using the appropriate suffix. The radixes that can be used to enter data into an instruction or data table element are: • • • • integer (D). binary (B). hexadecimal (H). octal (O). Numeric constants are used in place of data file elements. They cannot be manipulated by the user program.
E-20 Data File Organization and Addressing Addressing M0-M1 Files The addressing format for M0 and M1 files is below: Mf:e.s/b Where M = module f = file type (0 or 1) e = slot (1 to 30) s = word (0 to max. supplied by module) b = bit (0 to 15) Restrictions on Using M0 and M1 Data File Addresses M0 and M1 data file addresses can be used in all instructions except the OSR instruction and the instruction parameters noted below. Table E.
Data File Organization and Addressing Mf:e.s b Mf:e.s b Mf:e.s b Mf:e.s Mf:e.s L U b b E-21 f = file (0 or 1) When you are monitoring the ladder program in the run or test mode, the programming terminal does not show these instructions as being true when the processor evaluates them as true. SLC 5/03 and Higher Processors The SLC 5/03 and higher processors allow you to monitor the actual state of each addressed M0/M1 address (or data table).
E-22 Data File Organization and Addressing First scan bit. It makes this rung true only for the first scan after entering the Run mode. The COP instruction that follows copies data form an M1 data file to an integer file. This technique is used to monitor the contents of an M0 or M1 data file indirectly, in a processor data file. Access Time During the program scan, the processor must access the specialty I/O card to read/write M0 or M1 data.
Data File Organization and Addressing E-23 In the equivalent rungs of the following figure, XIC instruction M0:2.1/1 is used only in rung 1, reducing the scan time by approximately 1 ms. These rungs provide equivalent operation to those of figure A by substituting XIC instruction B3/10 for XIC instruction M0:2.1/1 in rung 2. Scan time is reduced by approximately 1 ms (SLC 5/02, Series B processor). The following figure illustrates another economizing technique.
E-24 Data File Organization and Addressing Capturing M0-M1 File Data The first two ladder diagrams in the last section illustrate a technique allowing you to capture and use M0 or M1 data as it exists at a particular time. In the first figure, bit M0:2.1/1 could change state between rungs 1 and 2. This could interfere with the logic applied in rung 2. The second figure avoids the problem. If rung 1 is true, bit B3/10 captures this information and places it in rung 2.
Data File Organization and Addressing E-25 This rung is true for the first scan after powerup to unlatch M0:2.1/1. G Data Files - Specialty I/O Modules Some specialty I/O modules use G (confiGuration) files (indicated in the specific specialty I/O module user’s manual). These files can be thought of as the software equivalent of DIP switches. The content of G files is accessed and edited offline under the I/O Configuration function. You cannot access G files under the Monitor File function.
E-26 Data File Organization and Addressing Notes: Publication 1747-RM001G-EN-P - November 2008
Appendix F Number Systems This appendix: • covers binary and hexadecimal numbers. • explains the use of a hex mask to filter data in certain programming instructions. Binary Numbers The processor memory stores 16-bit binary numbers. As indicated in the following figure, each position in the number has a decimal value, beginning at the right with 20 and ending at the left with 215. Each position can be 0 or 1 in the processor memory.
F-2 Number Systems 0111 1111 1111 1111 1x214 = 16384 1x213 = 8192 1x212 = 4096 1x211 = 2048 1x210 = 1024 1x29 = 512 1x28 = 256 1x27 = 128 1x26 = 64 1x25 = 32 1x24 = 16 1x23 = 8 1x22 = 4 1x21 = 2 1x20 = 1 32767 0x215 = 0 This position is always zero for positive numbers. Negative Decimal Values The 2s complement notation is used. The far left position is always 1 for negative values.
Number Systems 1111 1111 1111 F-3 1x214 = 16384 1x213 = 8192 1x212 = 4096 1x211 = 2048 1x210 = 1024 1x29 = 512 1x28 = 256 1x27 = 128 1x26 = 64 1x25 = 32 1x24 = 16 1x23 = 8 1x22 = 4 1x21 = 2 1x20 = 1 32767 1111 1x215 = 32768 This position is always 1 for negative numbers. Hexadecimal Numbers Hexadecimal numbers use single characters with equivalent decimal values ranging from 0 to 15.
F-4 Number Systems 218A 2x163 = 8192 1x162 = 256 8x161 = 128 10x160 = 10 8586 Hexadecimal and binary numbers have the following equivalence. Hexadecimal Binary 218A = 8586 0010 0001 1000 1010 8192 1x213 256 1x28 128 1x27 10 1x23+1x21 = 8586 Example Decimal number -8586 in equivalent binary and hexadecimal form. Binary 1101 Hexadecimal 1110 0111 DE76 0110 = -8586 = 56950 (negative number, -8586) Hexadecimal number DE76 = 13x163+14x162+7x161+6x160 = 56950.
Number Systems Hex Mask F-5 This is a 4-character code, entered as a parameter in SQO, SQC, and other instructions to exclude selected bits of a word from being operated on by the instruction. The hexadecimal values are used in their binary equivalent form, as indicated in the figure below. The figure also shows an example of a hexadecimal code and the corresponding mask word.
F-6 Number Systems Binary Floating-point Arithmetic The SLC 5/03, OS301 and higher, SLC 5/04, and SLC 5/05 processors support the use of floating-point. Use floating-point when you want to manipulate numbers outside of the range −32768 to +32767 or for a resolution finer than one unit. For example, 2.075. Floating-point arithmetic does not support non-normalized, Not a Number (NaN), and infinity. The valid range for a floating-point number is ±3.40282 x 1038 to ±1.
Appendix G Application Example Programs This appendix is designed to illustrate various instructions described previously in this manual. Application example programs include: • • • • paper drilling machine using most of the instructions. time driven sequencer using TON and SQO instructions. event driven sequencer using SQC and SQO instructions. on/off circuit using basic, program flow, and application specific instructions. • interfacing with enhanced bar code decoders over DH-485.
G-2 Application Example Programs OPERATOR PANEL Start I:1/6 Stop I:1/7 Change Drill Now Change Drill Soon O:3/4 Thumbwheel for Thickness in 1/4 in.
Application Example Programs Paper Drilling Machine Operation Overview G-3 Undrilled books are placed onto a conveyor taking them to a single spindle drill. Each book moves down the conveyor until it reaches the first drilling position. The conveyor stops moving and the drill lowers and drills the first hole. The drill then retracts and the conveyor moves the same book to the second drilling position. The drilling process is repeated until there are the desired holes per book.
G-4 Application Example Programs The following rung will call the drill sequence subroutine. The subroutine manages the operation the drilling sequence and will restars the conveyor upon completion of the drilling sequence. JSR Jump T o Subroutine SBR File Number 0003 The following rung will call the subroutine drill bit.
Application Example Programs G-5 Drill Mechanism Operation When the operator presses the start button, the drill motor turns on. After the book is in the first drilling position, the conveyor subroutine sets a drill sequence start bit, and the drill moves toward the book. When the drill has drilled through the book, the drill body hits a limit switch and causes the drill to retract up out of the book.
G-6 Application Example Programs Conveyor Operation When the start button is pressed, the conveyor moves the books forward. As the first book moves close to the drill, the book trips a photo-eye sensor. This tells the machine where the leading edge of the book is. Based on the position of the selector switch, the conveyor moves the book until it reaches the first drilling position. The drill sequence start bit is set and the first hole is drilled.
Application Example Programs G-7 The following rung will keep track of the hole number that is being drilled and loads the next correct DII preset based on the hole count. This rung is only active when the "HOLE SELECTOR" switch is in the "3-HOLE" position. The sequencer uses step 0 a s a null step upon reset. It uses the last step as a "go forever" in anticipation o f the "end of manual".
G-8 Application Example Programs The following rung is identical to the previous two rungs except that it is only active when the "HOLE SELECTOR" switch is in the "7-HOLE" position. I:1 I:1 SQO Sequencer Output File #N10:12 Mask 0FFFFh Dest S:50 Control R6:6 Length 8< Position 0< 0004 9 1746-IA16 10 1746-IA16 EN DN R6:6 U EN Discrete Input InterruptCompare Value MOV Move Source EQU Equal Source A R6:6.
Application Example Programs G-9 The following rung stops the conveyor and signals the main program (file 2) to initialize a drilling sequence. The DRILL SEQUENCE subroutine (program file 6) resets the drill sequence start bit and sets the conveyor drive bit (O:3/0) upon completion of the drilling sequence.
G-10 Application Example Programs Drill Calculation and Warning The program tracks the number of holes drilled and the number of inches of material that have been drilled through using a thumbwheel. The thumbwheel is set to the thickness of the book per 1/4 inch. (If the book is 1 1/2 inches thick, the operator would set the thumbwheel to 6.) When 25,000 inches have been drilled, the Change Drill Soon pilot light turns on. When 25,500 inches have been drilled, the Change Drill Soon pilot light flashes.
Application Example Programs The following rung will reset the number o f 1/4" increments RESET" keyswitch is energized. Drill Change Reset Keyswitch I:1 0001 8 1746-IA16 and the 1/4" thousands when the "DRILL CLR Clear Dest CLR Clear Dest BCD thumbwheel G-11 CHANGE N7:11 0< N7:10 0< input Thumbwheel Section Comment Bit B3:1 0002 2 The following rung will move the single digit BCD thumbwheel value into an internal integer register.
G-12 Application Example Programs The following rung will convert the BCD thumbwheel value from BCD to integer. This is done because the processor operates upon integer values. This rung also "debounces" the thumbwheel to ensure that conversion only occurs on valid BCD values. Note that invalid BCD values can occur while the operator is changing the BCD thumbwheel. This is due to input filter p ropagation delay differences between the 4 input circuits that provide the BCD input value.
Application Example Programs G-13 The following rung will keep a running total of how many inches of paper have been drilled with the current drill bit. Every time a hole is drilled, add the thickness (in ¼"s) to the running total (kept in ¼"s). The same OSR is necessary because the ADD will execute every scan that the rung is true, and the drill body would actuate the DRILL DEPTH limit switch for more than 1 program scan.
G-14 Application Example Programs The following application example illustrates the use of the TON and SQO instructions in a traffic signal at an intersection. The timing requirements are: Time Driven Sequencer Application Example • Red light - 30 seconds. • Yellow light - 15 seconds. • Green light - 60 seconds. The timer, when it reaches its preset, steps the sequencer that in turn controls which traffic signal is illuminated.
Application Example Programs Event Driven Sequencer Application Example G-15 The following application example illustrates how the FD (found) bit on an SQC instruction can be used to advance as SQO to the next step (position). This application program is used when a specific order of events is required to occur repeatedly. By using this combination, you can eliminate using the XIO, XIC, and other instructions. For a detailed explanation of: • XIC, XIO, and RES instructions, see Chapter 2.
G-16 Application Example Programs Table G.1 SQC Compare Data Addresses Data (Radix = Decimal) N7:0 0 1 2 3 4 5 6 7 8 9 N7:10 0 0 1 2 3 4 5 6 7 8 If the high-speed counter reached its high preset of 350 (indicates that the holding area reached maximum capacity), it would energize O:0/0, shutting down the filling operation. Before re-starting the filler, allow the packer to empty the holding area until it is about 1/3 full.
Application Example Programs G-17 On/Off Circuit Ladder Program Does a one-shot from the input push button to an internal bit - the internal bit is true for only one scan. This prevents toggling of the physical outpout in case the push button is held "ON" for more than one scan (always the case).
G-18 Application Example Programs The only devices capable of polling a slave device on DH-485 are the SLC 5/03 and higher processors. For the SLC 5/03 processors (1747-OS302, FRN10 or later), polling can be done via channels 0 and 1. For the SLC 5/04 processors (1747-OS401, FRN7 or later), channel 0 supports this capability. There are many ways to trigger bar code decoders to read a bar code label when a label is present.
Application Example Programs G-19 Table G.2 Result of Scanning a Valid Bar code Result of Scan Bar Code Decoder Response Good Read turns on its “Good Read” onboard When one of these two inputs output wired to the SLC processor to the SLC are turned on, the SLC will initiate a “MSG Read” turns on its “No-Read” onboard to the decoder to get the label output wired to the SLC processor data or no-read message data.
G-20 Application Example Programs Sequence of Events The photo switch input to the SLC goes from false-to-true The SLC processors send a “trigger” command to the decoder via a “MSG Write” command. The decoder immediately replies to the SLC that it has properly received the command. The decoder immediately replies to the SLC that it has properly received the command. The reply sets the MSG DN bit and clears the MSG DA bit in the SLC processor.
Application Example Programs G-21 Optimizing MSG Time-out If the time delay between sending a command to an Enhanced Bar Code Decoder and polling for the reply is not long enough, the MSG instruction will time-out (MSG TO bit = 1) each time it is enabled from that point forward. To re-synchronize the SLC processor and the decoder, you need to cycle power on the decoder to clear its buffer.
G-22 Application Example Programs Example Scanner and Decoder Configuration Table G.
Application Example Programs G-23 Example Ladder Program This rung detects the Photo Switch input going from false-to-true, and latches internal storage bit B3/1. This rung moves the decimal value for the bar code decoder “trigger” command into the MSG instructions “Offset” parameter. The programming software does not allow values greater than 255 decimal to be entered into a MSG control block “Offset” value.
G-24 Application Example Programs The internal storage bit, B3/1, holds the MSG instruction true until DN and DA are both set, indicating completion of the command sent and reply received sequence. When DN is set and DA is reset, unlatching the MSG EN bit effectively toggles the MSG instruction the same as if the MSG rung were toggled, i.e. rung conditions made false, then true.
Application Example Programs G-25 This rung moves the decimal value for the bar code decoder “Read” command into the MSG instruction’s “Offset” parameter. The programming software does not allow values greater than 255 decimal to be entered into a MSG control block “Offset” value. The internal storage bit, B3/2, gives the MSG instruction a false-to-true transition to send the initial command. The initial reply from an Enhanced Bar Code Decoder will result in MSG DN = 1 and MSG DA = 0.
G-26 Application Example Programs When the SLC processor sets both DN and DA for a MSG instruction, the MSG sequence to an Enhanced BAr Code Decoder is complete. In this case, the decoder has received the “Read” command and has formulated a reply to this command. Therefore, unlatch B3/2 at this time to be ready for the next “REad” request. In addition, when DN and DA are both set, this indicates that the data received with the read reply (except “no-read” data) is valid and may be buffered or used.
Appendix H Supported Read/Write Commands This appendix provides the read and write commands that are supported by the SLC 500 Fixed, SLC 5/01, SLC 5/02, SLC 5/03, SLC 5/04, and SLC 5/05 processors. Refer to the DF1 Protocol and Command Set Reference Manual, publication 1770-6.5.16, for additional command details. Supported Read/Write Commands Table H.
H-2 Supported Read/Write Commands Notes: Publication 1747-RM001G-EN-P - November 2008
Index Numerics 5/03 processors passthru examples 15-3 5/04 processors passthru examples 15-12 5/05 processors BOOTP configuration 13-31 embedded web server capability 13-35 passthru examples 15-18 A Absolute (ABS) 4-24 math instruction 4-24 access denied bit B-13 ACK timeout SLC 5/03, 5/04 or 5/05 13-52 active nodes B-35 Add (ADD) 4-5 math instruction 4-5 addressing defining for SLC 5/03, 5/04, and 5/05 13-58, 13-66, 13-71 indexed E-10 using mnemonics E-6 addressing modes D-1, D-2 direct addressing D-2 i
2 Index configuring SLC 5/05 13-31–13-34 using the Rockwell Utility 13-33 Broadcast write command 13-6 C capturing M0-M1 file data E-24 carry bit B-5 channel 0 modem lost B-24 SLC 5/03, 5/04, and 5/05 full-duplex station 13-50, 13-51, 13-79 SLC 5/03, 5/04, and 5/05 remote station 13-66, 13-71 channel configuration Modbus RTU Master parameters 13-93 channel-to-channel passthru 14-2 Clear (CLR) 4-12 math instruction 4-12 clock/calendar day B-54 clock/calendar hours B-54 clock/calendar minutes B-54 clock/
Index how counters work 2-13 CRC 13-52, 13-58, 13-66, 13-72, 13-80 creating data for indexed addresses E-11 crossing file boundaries E-11, E-15 current/last 10 ms scan time B-19 D data file organization and addressing 1-2, E-1 bit file 1-3 bit shift instructions E-16 control file 1-5 creating data for indexed addresses E-11 crossing file boundaries E-11, E-15 data file types E-3 data files ASCII file 10-3 string file 10-3 effects of program interrupt on S24 E-14 file copy and file fill instructions
4 Index Slot Number B-55 subroutine content 11-20 Discrete Input Interrupt Status File Accumulator B-56 Bit mask B-55 Compare Value B-56 Down Coun B-56 displaying values E-18 Divide (DIV) 4-9 math instruction 4-9 Double Divide (DDV) 4-11 math instruction 4-11 DTR control bit (channel 0) B-50 DTR force bit (channel 0) B-50 duplicate packet detection SLC 5/03, 5/04, and 5/05 13-52, 13-59, 13-67, 13-72 E embedded responses SLC 5/03, 5/04, and 5/05 13-52 ENC, Encode 1 of 16 to 4 5-11 Encode (ENC) 5-11 data
Index FRN 10 update A-19, A-21 FRN 6 update A-13 FRN 7 update A-15 FRN 9 update A-16 full-duplex station 13-51, 13-80 G G data files E-25 editing G file data E-25 Global Status File B-59 Global Status Word 13-19, 13-20 overview 13-18 status file B-59 transmit enable bit 13-19 transmit receive bit 13-20 going-to-run errors 16-4 H High-speed Counter (HSC) 2-15 addressing structure 2-16 application example 2-18, 2-19 counter instruction 2-15 I I/O addressing for a fixed controller E-6 for a modular control
6 Index major error halted bit B-12 manuals, related P-2 Masked Move (MVM) updates to arithmetic status bits 5-18 math instructions 4-2 32-Bit addition and subtraction 4-6 about 4-2 Absolute (ABS) 4-24 Add (ADD) 4-5 Arc Cosine (ACS) 4-29 Arc Sine (ASN) 4-29 Arc Tangent (ATN) 4-30 changes to the math register 4-3 Clear (CLR) 4-12 Compute (CPT) 4-25 Cosine (COS) 4-30 Divide (DIV) 4-9 Double Divide (DDV) 4-11 instruction parameters 4-2 Log to the Base 10 (LOG) 4-31 Multiply (MUL) 4-8 Natural Log (LN) 4-31 ov
Index radices used E-18 numeric constants E-18 NVRAM size B-58 O One-Shot Rising (OSR) entering parameters 2-5 operating system 16-15 catalog number B-57 downloading 16-15 FRN B-57 series B-57 size B-58 Or (OR) updates to arithmetic status bits 5-21 OTL, Output Latch 2-4 OTU, Output Unlatch 2-4 outgoing message command pending (channel 0) B-46 output data file 1-2 Output Energize (OTE) 2-4 basic instructions 2-4 output file E-2 Output Latch (OTL) 2-4 using 2-4 Output Unlatch (OTU) 2-4 using 2-5 overflow b
8 Index remote station address 15-2 reserved B-6, B-22, B-23, B-53, B-59 Reset (RES) 2-20 Retentive Timer (RTO) using status bits 2-12 retries SLC 5/03, 5/04, and 5/05 13-59, 13-67, 13-73 Return (RET) 6-3 nesting subroutine files 6-4 using 6-5 Return from Subroutine (RET) 6-5 program flow instruction 6-5 RIO Block Transfer Overview 8-2 RTS off delay 13-59, 13-67, 13-72, 13-89 RTS send delay 13-59, 13-67, 13-72, 13-89 runtime errors 16-6 S saved with single step test enabled bit B-14 Scale Data (SCL
Index T Tangent (TAN) 4-32 math instruction 4-32 test single step breakpoint B-40 start step on B-40 test-fault/powerdown B-41 timer accumulator value (.ACC) 2-7 timer accuracy 2-8 timer and counter instructions 1-5 accumulator value (.ACC) 1-7, 2-7 addressing structure 1-5 counters Count Up (CTU) 2-13, 2-14 High-Speed Counter (HSC) 2-15 Reset (RES) 2-20 how counters work 2-13 preset value (.
Publication 1747-RM001G-EN-P - November 2008
SLC 500 Alphabetical List of Instructions Instruction Page Instruction ABL - Test Line for Buffer 10-6 ENC - Encode 1 of 16 to 4 5-11 PID - Proportional/Intergral/Differential 9-3 ABS - Absolute 4-24 EQU - Equal 3-2 RAD - Degrees to Radians 5-9 ACB - Number of Characters In Buffer 10-7 FBC - File Bit Comparison 7-18 REF - I/O Refresh 6-10 ACI - String to Integer 10-8 FFL - FIFO Load 5-26 RES - Reset 2-20 FFU - FIFO Unload 5-26 RET - Return 6-3 ACL - ASCII Clear Receive and/or S
Rockwell Automation Support Rockwell Automation provides technical information on the Web to assist you in using its products. At http://support.rockwellautomation.com, you can find technical manuals, a knowledge base of FAQs, technical and application notes, sample code and links to software service packs, and a MySupport feature that you can customize to make the best use of these tools.
