Owner's manual

Module Block Diagram
B-1
A
PPENDIX
B
Module Block Diagram
WATCHDOG
LOGIC
40 MHz OSC
& RESET
LOGIC
20 MHz
DIV 2
10 MHz
20 MHz
MULTIBUS
CONNECTORS
P1 & P2 MULTIBUS SLAVE
INTERFACE
(XILINX-FPGA)
CPU
UNIVERSAL SERIAL
CONTROLLER
DUAL-PORT
SRAM
2K X 16
16
16
32
16
MEMORY
READ/WRITE
CONTROL
(0 WAIT-STATE SRAM)
SRAM
128K X 32
FLASH 1 FLASH 2
See note 1128K X 8
CH 1
RECV
CH1
XMIT
CH 2
RECV
CH 2
XMIT
MANCHESTER
DECODER
FIBER OPTIC
DRV/RCV
MANCHESTER
DECODER
FIBER OPTIC
DRV/RCV
CH 1
FIBER-OPTIC
CONNECTORS
CH 2
FIBER-OPTIC
CONNECTORS
8-BIT
XCVR/
BUFF
COUNTER/TIMER
MONITOR
INTERFACE
CIRCUITRY
(4) ANALOG
OUTPUT CHS.
MONITOR I/F
CONN.
ANALOG
OUTPUT
CONN.
FRONT PANEL
LEDS & SWITCHES
8 8 8
8
8832
FIBER OPTIC I/F
(FOR TEST PURPOSES)
SYNC CCLK LOGIC SLOT DECODE
CONTROL & ARBITRATION INTERRUPTS (4 OUT,1 IN)
32-BIT RISC 1KB DATA SRAM 4 DMA CHS. INTERRUPT CNTR.
(2) 10 Mbit CHS. 64 BYTE FIFO DMA SUPPORT MULTI-PROTOCOL CRC GEN/CHECK 16-BIT BUS I/F
APPLICATION LOCAL STORAGE NETWORK BUFFER
(3) 16-BIT COUNTERS
8-BIT D/A +/- 10V P-P 20 mA
(6) DRV STAT (2) TEST & FAULT LEDS SWITCHES
1 Flash 2 memory inUDC module B/M O-57552 = 12K x 8
Flash 2 memory in UDC EM module B/M O-57652 = 256K x 8