User Manual

6-16
AutoMax Network Communication Option Board
40 ANALOG TACH GAIN ADJ (P.201) Scales analog tachometer feedback signal gain * 1000
41
ANALOG TACH ZERO ADJ (P.202) Offset removed from analog tachometer feedback signal
42
ARM VOLTAGE GAIN ADJ (P.204) Scales the armature voltage signal gain * 1000
43
ARM VOLTAGE ZERO ADJ (P.205) Offset removed from armature voltage feedback
44
SPD LEADLAG RATIO (P.213) Ratio between low and high break frequencies of speed
feedback lead/lag block
45 SPD LEADLAG LOW FREQ (P.214) Low break frequency of speed feedback lead/lag block radians/second * 100
46
SPD LOOP LAG FREQ (P.215) Lag break frequency for the speed loop forward path lag
block
radians/second * 100
47
SPD LEADLAG SELECT (P.216) Speed/voltage loop lead/lag block select 0=LEAD/LAG; 1=BYPASS; 2=LAG/LEAD
48 SPD LOOP LAG BYPASS (P.217) Speed/voltage loop lag block bypass 0=OFF (not bypassed); 1=ON (bypassed)
49
CML FEEDBACK GAIN ADJ (P.300) Current minor loop feedback gain adjust gain * 1000
52
NETW COMM LOSS SELECT (P.901) Selects how the drive responds to network
communication loss
0=FAULT; 1=USE LAST REF; 2=USE TRMBLK
REF
Table 6.15 – FlexPak 3000 Alternate Register Map, Drop_3: Master Write Registers, FULL Connection. Configurable Data (Drive Input Data)
Register Bit Parameter Name (Number) Description Settings
50 TACH LOSS SCR ANGLE (P.608) SCR firing angle used in tach loss detection logic degrees
51
FIELD REF SELECT (P.521) Selects reference source for the field current regulator 0 = REGISTER; 1=ANALOG MAN TRIM REF;
2=
ANALOG IN 1; 3=ANALOG IN 2
53 0
NEG CUR LIM INV EN (P.226) Enables negative current limit inverter 0 = DISABLED; 1 = ENABLED
1 OCL PROP TRIM SELECT (P.813) Sets OCL output proportional to absolute value of speed
reference at the output of the speed loop S-curve block
0 = DISABLED; 1 = ENABLED
2 OCL TYPE3 POSN REG EN (P.814 Implements type 3 position regulator
3
STOP DECEL SELECT (P.122) Selects the deceleration time for ramp stop sequences 1=DECELERATION TIME; 2=RAMP STOP
DECEL TIME
4 Reserved
5
CML REF LIMIT SELECT (P.311) Source for CML positive and negative current limits 1=SPD LOOP PI LIMITS; 2=REGISTER
6 to 15 Reserved
Configurable data are read by the regulator approximately every 600 msec when Tune/Config Input Enable bit=1 and the drive is not running or jogging.
Table 6.14 – FlexPak 3000 Alternate Register Map, Drop_3: Master Write Registers, FULL Connection. Tunable Data (Drive Input Data) (Continued)
Register Bit Parameter Name (Number) Description Settings
Tunable data are read by the regulator approximately every 600 msec when Tune/Config Input Enable bit = 1.