USER MANUAL APS 6.0

Ladder Logic Program Basics
4–5
Inputs Output
Bit Status
Time XIC XIO OTE XIC XIO OTE
t
1
(initial) False True False 0 0 0
t
2
True
True Goes True 1 0 1
t
3
True False Goes False 1 1 0
t
4
False False Remains False 0 1 0
Types of Ladder Logic Connections
In a ladder logic diagram each of the input devices are represented in series or
parallel logic combinations across the rung of the ladder. The last element on the
rung is the output that receives the action as a result of the conditional state of the
inputs on the rung.
Series Logic
In the previous section on logical continuity , you have seen examples of series
(AND) logic. This means that when all input conditions in the path are true,
energize the output.
a
b
c
In the above example, if A and B are true, ener gize C.