Reference Manual

130 Rockwell Automation Publication PFLEX-RM003E-EN-E - January 2011
Chapter 1 Detailed Drive Operation
• Bit 7 “Enc0 EdgTime” or bit 23 “Enc1 EdgTime” configures the method of
sampling used by the Velocity Position Loop (VPL). Setting the bit
chooses “Edge to Edge” sampling, while resetting the bit to zero chooses
“Simple Difference” sampling. “Simple Difference” sampling calculates
speed by examining the difference between pulse counts over a fixed
sample time. “Edge to Edge” sampling adjusts the sample time to
synchronize with the position count updates from the daughter card -
improving the accuracy of the speed calculation.
• Bits 10…12 “En0SmplRt bx”, or bits 26…28 “En1SmplRt bx”, sets the
number of taps for a Finite Impulse Response (FIR) filter (see Table 17 -
FIR Filter Settings).
Table 15 - Encoder Input Filter Settings
Table 16 - Multiplier and Direction Settings
Table 17 - FIR Filter Settings
Bit 3/19 2/18 1/17 0/16 Encoder Bit Filter Settings
0 0 0 0 Filter disabled
0 0 0 1 100 ns filter
0 0 1 0 200 ns filter
0 0 1 1 300 ns filter
0 1 0 0 400 ns filter
0 1 0 1 500 ns filter
0 1 1 0 600 ns filter
0 1 1 1 700 ns filter
1 0 0 0 800 ns filter (default setting)
1 0 0 1 900 ns filter
1 0 1 0 1000 ns filter
1 0 1 1 1100 ns filter
1 1 0 0 1200 ns filter
1 1 0 1 1300 ns filter
1 1 1 0 1400 ns filter
1 1 1 1 1500 ns filter
Bit 5/21 4/20 Mult. Directions Comments
0 0 2x fwd/rev Counts rise/fall of phase A, phase B only used to find
direction
0 1 4x fwd/rev Counts rise/fall of both A and B phases (default setting)
1 0 1x fwd only Counts rise of phase A. Phase B ignored.
1 1 2x fwd only Counts rise of phase A. Phase B ignored.
Bit 12/28 11/27 10/26 Number of Taps
000 1
001 2
010 4
011 8
100 16
101 32
110 64
111 127