User manual

Instruction Set
Shift Register 3-33
shift register instructions continued...
Instruction Description
FIFO Load
FFL
Status Bits:
EN - Enable Load
DN - Done Bit
EM - Empty Bit
When the input conditions go from false-to-true, the processor loads N60:1 into the next
available element in the FIFO file, #N60:3, as pointed to by R6:51. Each time the rung goes from
false-to-true, the processor loads another element. When the FIFO file (stack) is full, (64 words
loaded), the DN bit is set.
FIFO Unload
FFU
Status Bits:
EU - Enable Unload
DN - Done Bit
EM - Empty Bit
When the input conditions go from false-to-true, the processor unloads an element from N60:3
into N60:2. Each time the rung goes from false-to-true, the processor unloads another element.
All the data in file #N60:3 is shifted one position toward N60:3. When the file is empty, the EM
bit is set.
FIFO LOAD
Source N60:1
FIFO #N60:3
Control R6:51
Length 64
Position 0
FFL
FIFO UNLOAD
FIFO #N60:3
Dest N60:2
Control R6:51
Length 64
Position 0
FFU