User manual

Hardware Components
Processor Status File 1-24
processor status file continued...
This word of the status file: Stores:
S:24 Indexed addressing offset
S:25 Reserved
S:261. User control bits
Bit
Description
0 Restart/continuous SFC: when reset, processor restarts at first step in SFC.
When set, processor continues with active step after power loss or change to RUN
1 Start-up protection after power loss: when reset, no protection.
When set, processor sets major fault bit S:11/5 when powering up in run mode
2 Define the address of the local rack: when reset, local rack
address is 0. When set, local rack address is 1
3 Set complementary I/O: when reset, complementary I/O is not
enabled. When set, complementary I/O is enabled
4 Local block transfer compatibility bit: when reset, normal
operation. When set, eliminates frequent checksum errors to
certain BT modules
5 PLC-3 scanner compatibility bit: when set (1), adapter channel
response delayed by 1 ms; when reset (0), operate in
normal response time
6 Data table-modification inhibit bit. When set (1), user cannot edit
the data table while processor is in run mode
S:27 Rack control bits:
• S:27/0-7 - - I/O rack inhibit bits for racks 0-7
• S:27/8-15 - - I/O rack reset bits for racks 0-7
See also S:7, S:32, S:33, S:34, and S:35.
S:28 Program watchdog setpoint