PLC 2/30 Programmable Controller Programming and Operations Manual
Important User Information Because of the variety of uses for this equipment and because of the differences between this solid state equipment and electromechanical equipment, the user of and those responsible for applying this equipment must satisfy themselves as to the acceptability of each application and use of the equipment. In no event will Allen-Bradley Company, Inc. be responsible or liable for indirect or consequential damages resulting from the use or application of this equipment.
Table of Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1.0 Introduction to This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 Complementary I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 Data Highway Compatibility . . . . . . . . .
ii Table of Contents 3.3.2 Instruction Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 Fundamental Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Data Table Documentation Forms . . . . . . . . . . . . . . . . . . . . . 3.4.1 Data Table Word Map (1024 Word) . . . . . . . . . . . . . . . . . . . 3.4.2 Data Table Map (128 Word) . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 Data Table Word Assignments (64 Word) . . . . . . . . . . . . . . . 3.4.
Table of Contents iii 5.4 Programming Timer and Counter Instructions . . . . . . . . . . . . . 5.5 Scan Time and Instruction Execution Times . . . . . . . . . . . . . . 5.5.1 Scan Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2 Program for Determining Scan Time . . . . . . . . . . . . . . . . . . 5.6 Instruction Execution Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.
iv Table of Contents 7.4.2 Independent Programming . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 I/O Update Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.1 Local Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.2 Remote Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 13 7 15 7 15 7 15 7 16 Peripheral Functions . . . . . . .
Table of Contents v 10.2.2 Block Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.3 File Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.4 Enable Bit and Done Bit . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 Instruction Notes for Block Transfer Read and Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 Causes of Run Time Errors . . . . . . . . . . . . . . . . . . . . . . . . . 10.
vi Table of Contents 12.5.1 Accessing the Data Monitor Mode . . . . . . . . . . . . . . . . . . . 12.5.2 Data Monitor Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.3 Cursor Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.4 Data Monitoring Procedures . . . . . . . . . . . . . . . . . . . . . . . 12.5.5 Entering and Changing Data . . . . . . . . . . . . . . . . . . . . . . . 12 21 12 24 12 25 12 26 12 27 Shift Register Instructions . . . . . . . . . . .
Table of Contents vii 15.3.1 Operation of the Sequencer Load Instruction . . . . . . . . . . . 15.3.2 Instruction Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.3 Programming the Sequencer Load Instruction . . . . . . . . . . 15 13 15 14 15 14 File Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1 16.0 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.1 File to File Logic Instructions . . . . . . . . . . . .
viii Table of Contents A.2.3 1/2 Slot Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.3 System Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 11 A 16 Number Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B 1 B.0 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.1 Decimal Numbering System . . . . . . . . . . . . . . . . . . . . . . . . . B.2 Octal Numbering System . . . . . . . . . . .
Chapter 1 Introduction 1.0 Introduction to This Manual This manual presents the information you need to program and operate your Allen-Bradley PLC-2/30 Programmable Controller. After reading this manual, you should be able to: establish system configurations consisting of: - scanners interface modules input modules output modules power supplies program: - timers counters extended arithmetic functions relay-type functions and data transfer, for a few examples.
Chapter 1 Introduction With a user-written program and appropriate I/O modules, the PLC-2/30 programmable controller can be used to control many types of industrial applications such as: Process control Material handling Palletizing Measurement and gauging Pollution control and monitoring The 1772-LP3 processor has a read/write CMOS memory that stores user program instructions, numeric values and I/O device status.
Chapter 1 Introduction Functional Block Instructions - Shift Register instructions - File-to-File and Word-to-File Logic instructions - File-to-File, Word-to-File and File-to-Word transfer instructions Binary to BCD and BCD to Binary conversions On-line programming Data Highway and Data Highway II compatible Sequencers Contact histogram Report generation 1.2 Capabilities The data table for the 1772-LP3 processor can be expanded to 8,064 words with an 8K memory or to 8,192 words with a 16K memory.
Chapter 1 Introduction 1.2.1 Complementary I/O When using a 1772-SD2 remote I/O scanner/distribution panel, the I/O device capacity can be increased from 896 to 1,792 I/O. The increase is accomplished through configuration of the racks and programming. For more information, refer to the Remote I/O Scanner/Distribution Panel Product Data (publication 1772-2.18). 1.2.
Chapter 1 Introduction WARNING: Do not use a 1770-T1 or 1770-T2 industrial terminal to edit or change a program or data table values in PLC-2/30 memory that were generated using a 1770-T3 industrial terminal. Block instructions and instructions with word addresses 4008 or greater will not be displayed properly (Figure 1.1). The ERR message may appear randomly in the user program at instructions and addresses that the -T1 and -T2 industrial terminals are not designed to handle.
Chapter 1 Introduction 1.4 Terms Used in This Manual We use the following terms to describe the various parts of your PLC-2/30 system. Chassis — a hardware assembly used to house PC devices such as I/O modules, adapter modules, processor modules, power supplies and some processors (PLC-2/02, -2/16 and -2/17, for example). I/O Group — The logical assignment of a specific input image table word and its companion output image table word to a rack location.
Chapter 2 Hardware Considerations 2.0 General This chapter describes only those hardware items required when programming or operating the PLC-2/30 programmable controller. For more complete hardware information, refer to the PLC-2/20, PLC-2/30 Programmable Controller Assembly and Installation Manual (publication no. 1772-6.6.2). 2.1 Mode Select Switch A four-position mode select switch (Figure 2.1) is located on the front of the processor.
Chapter 2 Hardware Considerations Figure 2.1 PLC 2/30 Processor Diagnostic Indicators 2.2 Memory Write Protect 2 2 Keylock Mode Select Switch When the memory write protect jumper (Figure 2.2) is removed from a 1772-LH processor interface module, data table values can be changed between word addresses 0108 and 3778. These values can be changed only when the processor is in the program mode or in the run/program mode using on-line data change.
Chapter 2 Hardware Considerations Figure 2.2 Memory Write Protect Jumper HALFTONE WITH CALLOUT The remaining words in memory from 4008 to the end of memory, including data table and user program, are protected and cannot be altered by programming. The memory write protect feature guards against unintentional changes to processor memory. 2.
Chapter 2 Hardware Considerations modes, program or remote program. (If the keyswitch is in RUN/PROGRAM position, the industrial terminal automatically puts the processor into remote program mode. If the keyswitch is in the RUN position, or when it is connected to the processor through the 1771-KA2 communications adapter module, you must manually change the keyswitch to the PROGRAM position). WARNING: Forces are immediately removed if a Run-time error occurs.
Chapter 2 Hardware Considerations PROCESSOR FAULT — Illuminates when the logic circuits controlling the processor scan fail or if processor error or run-time errors occur which cause the processor to halt operation. If the processor fault is a run-time error, the industrial terminal will display RUN TIME ERROR when the keyswitch is in the PROGRAM or RUN/PROGRAM position. RUN — Illuminates when the processor is in the run or run/program mode.
Chapter 2 Hardware Considerations When using remote I/O (the 1772-SD2 scanner and the 1771-ASB remote I/O Adapter), these switches will be set according to the adapter module’s requirements. 2.6.1 Last State Switch The last state switch (switch no. 1) on the 1771 I/O chassis must be properly set. ON indicates that the outputs are left in their last state when a fault is detected. Machine operation can continue after fault detection.
Chapter 2 Hardware Considerations Figure 2.3 1771 I/O Chassis Backplane Switch Settings for Local I/O Systems No significance should be set to OFF On: Off: Outputs remain in last state when fault is detected. Outputs de energized when fault is detected. 2.
Chapter 2 Hardware Considerations on the front panel of the local adapter module aid in troubleshooting. These indicators are: ACTIVE — Illuminates when proper communication is established between the processor and the I/O chassis. It also indicates that DC power is properly supplied to the I/O chassis. It is normally on. RACK FAULT — Illuminates when I/O data is not in the proper format. It is normally off.
Chapter 2 Hardware Considerations Three diagnostic indicators are located on the front of the 1771-ASB adapter. These indicators are: ACTIVE — Illuminates when proper communications have been established between the 1772-SD2 distribution panel and the 1771-ASB adapter, DC power is properly supplied to the I/O chassis and 1771-ASB adapter is actively controlling the I/O. The ACTIVE indicator is normally on. ADAPTER FAULT — Illuminates when the module is not operating properly.
Chapter 2 Hardware Considerations CAUTION: For proper system data communications, a local/remote system structure with 2 local racks, you must use a 1777-CA cable (3 ft./.92m) between the processor and the two local racks. You must also use the 1772-CS cable (3 ft./.92m) from the second local rack to the distribution panel. 2.11 Hardware Addressing Modes The term “addressing mode” refers to the method of hardware addressing within individual I/O chassis.
Chapter 2 Hardware Considerations 2.12.2 1777 P2 Auxiliary Power Supply The 1777-P2 Series C power supply provides 9 amperes to power one or two bulletin 1771-I/O chassis. This includes the I/O adapter and the I/O modules in each chassis. The power supply must be used to power the 1772-SD2 distribution panel when the PLC-2/30 processor contains a core memory module. This power supply may be operated from either a 120 or a 220/240V AC source. 2.12.
Chapter 3 Data Table 3.0 General This chapter introduces concepts and terminology necessary for a general understanding of programmable controller memory. It explains the memory organization of the PLC-2/30 programmable controller. 3.1 Memory Structure The memory of the processor can be thought of as a large arrangement of storage points, each called a BInary digiT, or bit (Figure 3.1). A bit is the smallest unit of information a memory is capable of retaining.
Chapter 3 Data Table A group of 16 bits makes up a word. This word can be thought of as being made up of two 8-bit bytes; a lower byte and an upper byte. Because of its function in memory, one PLC-2/30 word may also be thought of as a memory location: when a word is being used, an actual physical location in memory is being accessed. A specific bit in memory can be identified by combining the word address and bit number to form the bit address, such as 030/12 or 1701/04.
Chapter 3 Data Table Figure 3.2 PLC 2/30 Memory Organization (Expanded Data Table) Total Decimal Words 8 Octal Word Address Decimal Words Per Area 8 Processor Work Area No. 1 Rack 1 010 017 000 007 010 Rack 2 020 0271 Output Image Table Rack address areas that are not configured as output image table become available for timer/counter accumulated values or word/bit storage. Rack 3 030 037 Rack 4 040 047 Rack 5 050 057 Rack 6 060 067 64 72 56 8 Rack 7 070 077 Processor Work Area No.
Chapter 3 Data Table The first 128 words of the memory are set aside for data table storage. This number includes 32 words for I/O image tables (i.e., 2 full racks), 16 words for processor work areas and 80 words for timers/counters. If timers/counters are not required, you can reduce the data table to 48 words. Expansion is in increments of two words until a table of 256 is reached, and then in increments of 128 words.
Chapter 3 Data Table These memory locations cannot be accessed by the user. Their word addresses are not available for addressing of any kind. The processor uses both areas for internal control functions. Output Image Table The primary function of the output image table is to control the status of outputs wired to the output modules. If the output image table bit is on, its corresponding output is on. If the bit is cleared to off, its corresponding output is off.
Chapter 3 Data Table CAUTION: Word 027 is reserved for processor use. Do not put block transfer or output modules in rack 2, I/O group 7. Timer/Counter Accumulated Values, Bit/Word Storage This area of memory is used to store accumulated values of timer/counter instructions. The area may also be used as storage for words and/or bits. Word addresses 0308 to 0778 bound this area when memory is configured for 256 I/O (maximum) and 40 Timer/Counter Instructions (Figure 3.3).
Chapter 3 Data Table CAUTION: If a remote I/O configuration is being used, words 1258 and 1268 may be used to store remote I/O fault bits. If this is the case, input modules must not be placed in these slots (rack 2, I/O groups 5 and 6): unexpected machine operation may result.
Chapter 3 Data Table Figure 3.3 PLC 2/30 Memory Organization (Default Configuration) Total Decimal Words Bit Octal Word Address Address Decimal Words Per Area 000 00 Processor Work Area No. 1 8 8 007 010 17 00 026 17 027 030 1 Output Image Table 24 16 00 Timer/Counter Accumulated Values (ACC) Internal Storage 64 40 077 100 17 00 107 110 17 00 125 2 126 127 130 17 00 177 17 Default Configured Data Table (128 Words) Processor Work Area No.
Chapter 3 Data Table Each bit in the input image table may have a corresponding real hardware terminal on the I/O rack associated with it, although this may not always be the case, since a corresponding input module may not actually be placed in an I/O rack slot. If it does, the terminal address is the same as the bit address. The correspondence between the two is illustrated in Figure 3.4. CAUTION: Bit and/or word storage is not possible in the input image table.
Chapter 3 Data Table Figure 3.
Chapter 3 Data Table Timer/Counter Preset Values, Bit/Word Storage This area of memory is used to store preset values of timer/counter instructions. The area may also be used as storage for words and/or bits. Word addresses 1308 to 1778 bound this area when memory is configured for 256 I/O (maximum) and 40 Timer/Counter Instructions (Figure 3.3).
Chapter 3 Data Table Table 3.A Data Table Configuration Function Mode Key Sequence Description Data Table Configuration Program [SEARCH] [5][0] [Numbers] If the number of 128 word sections is 1 or 2, enter this number, the number of I/O racks, and the number of timers/counters. If the number of 128 word sections is 3 or greater, enter only this number and the number of I/O racks. The industrial terminal will calculate and display the data table size in decimal.
Chapter 3 Data Table After you have determined the layout of the data table, press [SEARCH] [5] [0]. The following display appears: NUMBER OF 128-WORD DATA TABLE SECTIONS NUMBER OF I/O RACKS NUMBER OF TIMERS/COUNTERS (IF APPLICABLE) DATA TABLE SIZE The number of 128-word data table sections, the number of I/O racks (1-7), and the number of timers/counters (if applicable) to be entered is prompted by a reverse-video cursor.
Chapter 3 Data Table After the number of I/O racks is selected, the industrial terminal will compute and enter the data table size. Anytime you reduce the size of the data table, the processor searches for instructions in those areas. If an instruction exists in an area to be deleted, the change will not be allowed and the following message will be displayed: “INSTRUCTION EXISTS IN DELETED AREA.” To display the rung that is preventing the change, press [SEARCH].
Chapter 3 Data Table additional 7 timer/counter instructions become available. The previous output image table addresses 0208-0268 are now reserved for timer/counter accumulated values; previous input image table addresses 1208-1268, for timer/counter preset values. When I/O requirements are increased from the standard value of 256 to 384 (or from 2 racks to 3 racks), data table size does not change. Instead, timer/counter areas (in the default memory configuration) are each reduced by 8 words.
Chapter 3 Data Table 3.2.2 User Program You program is a group of ladder diagram instructions used to control an application. It is initially entered into memory using an industrial terminal. Main Program The main program follows the data table in memory and stores all the user program instructions that make up the ladder diagram program. Most instructions are stored in one memory word. Some advanced instructions require up to 8 memory words.
Chapter 3 Data Table 3.2.3 Message Storage Area The message storage area begins after the END of user program statement and it stores the alphanumeric characters of the messages. The memory is capable of storing user-programmed messages for hardcopy printout by compatible RS-232C data terminals. As many as 70 messages of varying length can be stored (198 messages can be stored when using the 1770-RG Report Generation module).
Chapter 3 Data Table If a bit is off (0), its corresponding output device is off (de-energized). Output image table bits are controlled by user program instructions. 3.3.2 Instruction Address Instruction addresses in the input/output (I/O) image tables take the form of Figure 3.5. These addresses have a dual role. Each 5-digit address corresponds (1) to an input or output table word (address) and (2) to a hardware location. Figure 3.
Chapter 3 Data Table Figure 3.5 Instruction Address Terminology Concept Example Hardware Terminology Hardware Terminology Word Address Input (1) or Output (0) Output: 0 Rack No. (1 7) Rack No.: 1 I/O Group No. (0 7) I/O Group No.: 0 Terminal No. (00 07, 10 17) Terminal No.
Chapter 3 Data Table Figure 3.
Chapter 3 Data Table 3.3.3 Fundamental Operation The hardware-program interface is illustrated in Figure 3.7 by showing the operational relationship between the input and output devices, the input/output image table and the user program. When an input device connected to terminal 113/12 is closed, the input module circuitry senses a voltage. The On condition is reflected in the input image table bit 113/12. During the program scan, the processor examines bit 113/12 for an On (1) condition.
Chapter 3 Data Table Figure 3.7 Relationship of Word Address to Hardware 3 Digit Word Addresses 2-Digit Bit and Terminal Address 17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00 0108 0 1 1 0 0 0 0128 Output Module in Assigned I/O Rack No. 1, I/O Group No. 2 Output Image Table Input Module in I/O Rack No. 1, I/O Group No.
Chapter 3 Data Table 3.4 Data Table Documentation Forms As you program your application, you should carefully record the data table addresses of the program elements. The importance of this documentation cannot be overemphasized. You will find it invaluable for avoiding improper use of data table areas and as an aid in troubleshooting and making program changes. The data table documentation forms presented at the end of this chapter can be reproduced or revised as needed.
Chapter 3 Data Table Figure 3.8 Example of Data Table Word Map WORD ADDRESS FROM 000 040 100 140 200 240 (32 WORDS) Outputs Storage Timer/Counter Not Used Inputs Timer/Counter Files Storage AC Values Storage PR Values TO Block Xfer Storage Block Xfer Storage WORD ADDRESS 037 077 137 177 237 277 300 3.4.2 Data Table Map (128 Word) This form can be used to log the bit status of a word and to describe the function of groups of related words within a 128–word data table section.
Chapter 3 Data Table Figure 3.9 Example of Data Table Map STARTING WORD ADDRESS 00 2 BIT NUMBER 17 2 10 07 00 DESCRIPTION 00 01 36 37 40 41 42 43 44 45 46 47 0 0 0 1 1 0 1 0 1 1 0 1 A 2 C 5 0 0 1 0 1 1 1 1 0 0 1 0 1 0 0 1 C 4 3 B 1 1 1 0 0 1 0 0 1 1 0 1 1 0 1 0 3 F D 4 0 1 0 1 1 0 1 0 1 0 0 1 1 0 1 0 B 8 5 E 1 1 0 0 FFM 062 (Binary) FFM 063 (Hex) 50 51 3.4.
Chapter 3 Data Table Figure 3.10 Example of Data Table Word Assignments WORD ADDR 20 DESCRIPTION 0 1 WORD ADDR Master cycle time, AC Drillhead #1, dwell time, AC 30 DESCRIPTION 0 1 Master cycle time, PR Drillhead #1, dwell time, PR 2 4 5 6 5 No. of passes, AC No. of reject parts, AC 6 No. of passes, PR No. of reject parts, PR 7 3.4.4 Data Table Bit Assignments This form can be used to log the function of input, output and storage bits.
Chapter 3 Data Table 3.4.5 Sequencer Table Bit Assignments This form can be used for any one of the three Sequencer instructions to log the data associated with each step. This information added to the heading of the assignment sheet should be identical to the information displayed in the data monitor mode heading and in the ladder diagram mode instruction block of the sequencer instruction. The mask row is used to log mask data, if required. The remaining rows are for logging the data of each step.
Chapter 3 Data Table Figure 3.
Chapter 3 Data Table placement can be found in the PLC-2/20, PLC-2/30 Programmable Controller Assembly and Installation Manual (publication no. 1772-6.6.2). 3.4.7 Timer/Counter Assignments In addition to I/O assignments, timers and counters must also be assigned data table word addresses. It is best to make a list of the word addresses used for timers and counters on data table documentation forms. Later, when sizing the data table, this list will be useful.
Chapter 3 Data Table Output image table words can be used for storage when the corresponding input image table words are used for nonblock transfer input modules. However, when there is a vacant I/O group or slot in the I/O chassis, do not use image table words for storage. This will allow room for future system expansion. Bits 14-17 of a timer or counter preset word can be used for bit storage, provided data is not transferred to the preset word by a Get/Put transfer or the timer is not set for a 0.
3 31 ALLEN-BRADLEY Connection Diagram Addressing BULLETIN 1771 I/O Chassis (8-point Modules) Chapter 3 Data Table PROJECT NAME PAGE DATE DESIGNER OF
3 32 Chapter 3 Data Table Bulletin 1771 I/O Chassis CONNECTION DIAGRAM ADDRESSING WORKSHEET (16-point Modules) PAGE DATE ÍÍ ÍÍÍÍ PROJECT NAME DESIGNER OF
ALLEN-BRADLEY Programmable Controller Chapter 3 Data Table DATA TABLE WORD MAP (1024 WORD) PROJECT NAME PROCESSOR DESIGNER DATA TABLE SIZE WORD ADDRESS FROM (32 WORDS) TO PAGE OF ADDRESS TO WORD ADDRESS 000 037 040 077 100 137 140 177 200 237 240 277 300 337 340 377 400 437 440 477 500 537 540 577 600 637 640 677 700 737 740 777 000 037 040 077 100 137 140 177 200 237 240 277 300 337 340 377 400 437 440 477 500 537 540 577 600 637 640
Chapter 3 Data Table ALLEN-BRADLEY Programmable Controller DATA TABLE WORD MAP (128 WORD) PROJECT NAME PROCESSOR DESIGNER DATA TABLE SIZE 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17 20 21 22 23 24 25 26 27 30 31 32 33 34 35 36 37 40 41 42 43 44 45 46 47 50 51 52 53 54 55 56 57 60 61 62 63 64 65 66 67 70 71 72 73 74 75 76 77 3 34 17 PAGE OF ADDRESS TO STARTING WORD ADDRESS STARTING WORD ADDRESS 00 00 BIT NUMBER BIT NUMBER 10 07 00 DESCRIPTION 00 01 02 03 04 05 06 07 10 11 12 13 14 1
ALLEN-BRADLEY Programmable Controller DATA TABLE WORD ASSIGNMENTS (64 WORD) PROJECT NAME PROCESSOR DESIGNER DATA TABLE SIZE WORD ADDR DESCRIPTION WORD ADDR Chapter 3 Data Table PAGE OF ADDRESS TO DESCRIPTION 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 Comments 3 35
Chapter 3 Data Table ALLEN-BRADLEY Programmable Controller DATA TABLE BIT ASSIGNMENTS PROJECT NAME PROCESSOR DESIGNER DATA TABLE SIZE WORD Comments 3 36 BIT DESCRIPTION WORD BIT 0 0 0 0 0 1 0 1 0 2 0 2 0 3 0 3 0 4 0 4 0 5 0 5 0 6 0 6 0 7 0 7 1 0 1 0 1 1 1 1 1 2 1 2 1 3 1 3 1 4 1 4 1 5 1 5 1 6 1 6 1 7 0 0 1 7 0 0 0 1 0 1 0 2 0 2 0 3 0 3 0 4 0 4 0 5 0 5 0 6 0 6 0 7 0 7 1 0 1 0 1 1 1 1 1 2 1 2 1 3 1 3 1 4 1 4 1 5 1 5 1 6 1 6 1 7 1 7 PAG
ALLEN-BRADLEY Programmable Controller Chapter 3 Data Table SEQUENCER TABLE BIT ASSIGNMENTS PROJECT NAME PROCESSOR DESIGNER DATA TABLE SIZE PAGE OF SEQUENCER COUNTER ADDR: FILE to SEQ LENGTH WORD ADDR: MASK ADDR: WORD #1 17 D E V I C E 10 07 WORD #2 00 17 10 07 WORD #3 00 17 10 07 WORD #4 00 17 10 07 00 N A M E MASK STEP FROM ADDR TO ADDR 3 37
Chapter 4 Introduction to Programming 4.0 General The user’s program is a group of ladder diagram and functional block instructions used to control an application. It is initially entered in memory using an industrial terminal. Assuming that the data table size has not been changed from factory-configured values, the user program begins after word address 1778.
Chapter 4 Introduction to Programming 4.2 Ladder Diagram Logic Programmable controller ladder diagram logic closely resembles hardwired relay logic. Hardwired relay control systems require electrical continuity to turn output devices on and off. For example, the relay diagram in Figure 4.1 shows that limit switch LS1 and relay contact CR2 must be closed to energize relay coil CR4. Figure 4.
Chapter 4 Introduction to Programming 4.3 Relay Type Instructions Programmable controllers have many of the capabilities of hardwired relay control systems. Control functions similar to those available with relays are provided by the following relay-type instructions: Examine instructions Output instructions Branch instructions 4.3.
Chapter 4 Introduction to Programming The condition of the Examine On instruction is either true or false: True – the addressed memory bit is one, meaning that the corresponding I/O device or bit is on False – The addressed memory bit is zero, meaning that the corresponding I/O device or bit is off When using the Examine On instruction to address an input device, the conventional normally open or normally closed distinctions are not made.
Chapter 4 Introduction to Programming Figure 4.5 Examine Off Instruction 112 |/| 05 4.3.2 Output Instructions 012 ( ) 14 The output instructions set an addressed memory bit to one (on) or reset it to zero (off). An output image table bit, as one or zero, can cause an output device to be turned on or off. Output instructions are programmed at the end of the ladder-diagram rungs (Figure 4.3). Only one output instruction can be programmed on each rung.
Chapter 4 Introduction to Programming CAUTION: The Output Energize instruction can be programmed unconditionally for some types of specialized programming. Its use should be limited to storage bits for these special purposes. An unconditional output energize instruction (Figure 4.7) causes the output instruction to remain energized continuously. This may not be desirable in output device programming. Figure 4.6 Output Energize Instruction 112 | | 06 012 ( ) 15 Figure 4.
Chapter 4 Introduction to Programming by an Output Unlatch instruction. If power is lost and back-up battery for CMOS RAM memory is maintained, all latched bits will remain on. The Output Unlatch instruction is used to de-energize a memory bit that has been latched on. The Output Unlatch instruction addresses the same memory bit that has been latched on (Figure 4.8). When the rung conditions for the Output Unlatch instruction go true, the addressed memory bit is reset to zero (off) (Figure 4.9).
Chapter 4 Introduction to Programming When the Mode Select Switch is changed from the RUN or RUN/PROG position, the last true Output Latch or Output Unlatch instruction continues to control the addressed memory bit, but disables the output device. When the Mode Select Switch is turned back to RUN or RUN/PROG position, a latched output device will be energized. The Output Latch and Unlatch instructions, when entered, are automatically set off.
Chapter 4 Introduction to Programming 4.3.3 Branch Instructions The branch instructions allow more than one combination of input conditions to energize an output device (Figure 4.11). These are two branch instructions: Branch Start Branch End Figure 4.11 Branching Instructions Two Branch Start Instructions A Single Branch End Instruction 111 | | 11 111 | | 12 010 ( ) 00 Two Possible Paths for Logic Continuity (OR Logic) Branch Start This instruction begins each parallel logic branch of a rung.
Chapter 4 Introduction to Programming Figure 4.12 Nested Branching vs. Equivalent Logic A | | B | | C | | ( ) D | | Branch Within a Branch E | | A. Desired Logic (Cannot be Programmed) A | | B | | C | | D | | C | | ( ) Instruction Repeated E | | B. Equivalent Logic (Can be Programmed) WARNING: While inserting a BRANCH START instruction to an existing rung during on-line programming, the actual output status (ON or OFF) may not be the logically expected state of the rung.
Chapter 4 Introduction to Programming Figure 4.13 Example Original Rung With First Part of Duplicate Rung 110 | | 00 110 | | 01 110 |/| 02 110 | | 00 110 | | 01 110 |/| 02 010 ( ) 00 Original Rung Added Rung With No Output 2. Cursor to the point where you want to change the logic and insert the BRANCH START. 3. Insert the desired parallel logic (see Figure 4.14). 4. Insert the BRANCH END. Figure 4.14 Example New Rung With Branch Instruction 110 | | 00 110 | | 01 110 |/| 02 110 |/| 03 5.
Chapter 4 Introduction to Programming This procedure allows the processor to make a smooth transition from one form of the rung to the other form during the time the branch start instruction is being completed. 4.3.4 Ending a Program The PLC-2/30 controller does not require that an END (of program) statement be entered by the user after the last program instruction. An END statement is generated by the processor.
Chapter 4 Introduction to Programming 4.3.5 Programming Relay Type Instructions WARNING: Use only Allen-Bradley authorized programming devices to program Allen-Bradley programmable controllers. Using unauthorized programming devices may result in unexpected operation, possibly causing equipment damage and/or injury to personnel.
Chapter 4 Introduction to Programming Table 4.A Relay Type Instructions NOTE: Examine and Output addresses, XXX/XX, can be assigned to any location in the Data Table, excluding the processor work areas. The word address is displayed above the instruction and the bit number below it. To enter a bit address larger than 5 digits, press the [EXPAND ADDR] key after the instruction key and then enter the bit address. Use a leading zero, if necessary.
Chapter 4 Introduction to Programming 4.4.1 Addressing The ladder diagram instructions are entered with the processor in the program mode. When entered, they are displayed as intensified and blinking to indicate cursor position and that information is needed. When entering addresses and data, the reverse-video character cursor can be manipulated to the left and right using the [←] and [→] keys to make corrections.
Chapter 4 Introduction to Programming Table 4.B Help Directories Function Mode Key Sequence Description Help Directory Any [HELP] Displays a list of the keys that are used with the [HELP] key to obtain further directories. Control Function Directory Any [SEARCH] [HELP] Provides a list of all control functions that use the [SEARCH] key. Record Function Directory Any [RECORD] [HELP] Provides a list of functions that use the [RECORD] key.
Chapter 4 Introduction to Programming entered is the word address for the Output instructions. The industrial terminal will locate all uses of the word addresses associated with the word address except for –| |– and–|/|–. Table 4.C SEARCH Functions Function Mode Key Sequence Description Locate first rung of program Any [SEARCH] [↑] Positions cursor on the first instruction of the program.
Chapter 4 Introduction to Programming If found, the rung containing the first occurrence of the address and/or instruction will be displayed as well as the rungs after it. If the SEARCH key is pressed again, the next occurrence of the address and/or instruction will be displayed. When it cannot be located or all addresses and/or instructions have been found, a NOT FOUND message will be displayed.
Chapter 4 Introduction to Programming The cursor will go directly to the first rung from anywhere in user program by pressing the [SEARCH][↑] keys. When the [SEARCH][↓] key sequence is pressed, the display will go to the next boundary in the first section indicated. By pressing the [SEARCH][↓] key sequence again, a subsequent boundary will be displayed until the user program end statement is reached. Boundaries will be displayed at the top of the screen with subsequent program rungs displayed beneath.
Chapter 4 Introduction to Programming Table 4.D Editing Functions1 Function Mode Key Sequence Description Inserting a Condition Instruction Program [INSERT] [Instruction] [Address] or [INSERT] [←] [Instruction] [Address] Position the cursor on the instruction that will precede the instruction to be inserted. Then press key sequence.2 Position the cursor on the instruction that will follow the instruction to be inserted. Then press key sequence.
Chapter 4 Introduction to Programming the instruction will be inserted before the END statement or subroutine area. The other way to insert an instruction is to press the key sequence [INSERT] [←] [Key sequence of instruction] [Key sequence of address]. The new instruction will be inserted before the cursor’s present position. Bit addresses of 6 or 7 digits can be entered provided the data table is expanded to a 4- or 5-digit word address and the [EXPAND ADDR] key is used.
Chapter 4 Introduction to Programming unlatch instructions are cleared to zero. All other word and bit addresses are not cleared when a rung is removed. Changing Data of a Word or Block Instruction The data of any word or block instruction, except the Arithmetic and Put instructions, can be changed in the program mode without removing and re-entering the instruction. This is done by positioning the cursor on the appropriate word instruction and pressing [INSERT][Data Digits].
Chapter 4 Introduction to Programming WARNING: When the address of an instruction whose data is to be changed duplicates the address of other instructions in the user program, the consequences of the change of each instruction should be thoroughly explored beforehand. NOTE: When the memory write protect is activated by removing the write protect jumper, on-line data change will not be allowed for addresses above 377.
Chapter 4 Introduction to Programming 2. Block Transfer Read and Write instructions, Jump, Jump to Subroutine, MCR, ZCL and Temp End instructions cannot be inserted. 3. The Label instruction cannot be inserted or removed directly, nor can the rung containing it be removed. However, the Label instruction can be changed to another instruction. CAUTION: When editing out a Label instruction, all Jump and Jump to Subroutine instructions with the same label number must be removed.
Chapter 4 Introduction to Programming WARNING: When the address of a new instruction duplicates the address of other instructions in the program, the [DATA INIT] key should not be used without first assessing the consequences. Pressing the [DATA INIT] key will zero out the status bits stored at the existing instructions address, which may interfere with desired machine operation. Damage to equipment and/or personal injury could result.
Chapter 4 Introduction to Programming [RECORD] key is used to enter a change into user program. Once pressed, the changed program is active immediately. [CANCEL COMMAND] key can be used to abort any on-line programming operation prior to pressing the [RECORD] key. It restores the ladder diagram display and program logic to its original state prior to the on-line programming operations. It is also used to terminate on-line programming mode. [DATA INIT] key should be used as described in Section 4.4.
Chapter 4 Introduction to Programming Step 1 – Press [DISPLAY] 0 or 1 for data monitor mode. Step 2 – Press [SEARCH] 51 for on-line data change. Step 3 – Enter file data, if necessary. Step 4 – Press [CANCEL COMMAND] to terminate on-line data change. Step 5 – Verify file data and/or data words. Step 6 – Press [CANCEL COMMAND] to terminate data monitor mode. Remove an Instruction A condition instruction can be removed using the following procedure (refer to Editing, Section 4.4.
Chapter 4 Introduction to Programming CAUTION: If the rung logic is true, the output instruction will be enabled immediately. Before pressing the [RECORD] key for the output instruction, verify that each instruction has been entered with no errors. Remove a Rung A completed rung can be removed using the following procedure (refer to Editing, Section 4.4.4, if necessary): Step 1 – Position the cursor on any instruction in the rung.. Step 2 – Press [REMOVE][RUNG][RECORD].
Chapter 4 Introduction to Programming data has been entered using the data monitor mode. See Insert an Instruction, above. WARNING: When the [RECORD] key is pressed, the substituted instruction is entered into memory immediately. If the rung is true, the output instruction will be enabled and will instantly energize the output device. Damage to equipment and/or personal injury could result. NOTE: Bit values and the data of word instructions are not cleared when an instruction is replaced by another.
Chapter 4 Introduction to Programming The rung will become active immediately. Programming Interruptions If communication between the industrial terminal and processor is interrupted when programming on-line in run/program mode, a rung could be left incomplete (no output instruction). Upon initialization of the industrial terminal, if an incomplete rung is thought to exist, proceed as follows: Step 1 – Locate the incomplete rung using the key sequence [SHIFT][SEARCH].
Chapter 4 Introduction to Programming Table 4.E Clear Memory Functions1 Function Mode Key Sequence Description Data Table Clear Program [CLEAR MEMORY] [7] [7] Displays a start address and an end address field. [Start Address] [End Address] Start and end word addresses determine boundaries for Data Table clearing. [CLEAR MEMORY] Clears the Data Table within and including addressed boundaries.
Chapter 4 Introduction to Programming Total Memory Clear The complete memory can be cleared by positioning the cursor on the first instruction of the program and then pressing [CLEAR MEMORY] 99. This resets all the data table bits to zero. A total memory clear should be done before entering the user program. 4.5 Program Recommendations The program recommendations listed below for constructing a ladder diagram rung should be considered.
Chapter 4 Introduction to Programming Figure 4.16 Storage Bit Example Exceeds Horizontal Display Limit 1 | | 2 | | 3 | | 4 | | 5 | | 6 | | 7 | | 8 | | 9 | | 10 | | 11 | | 12 | | 13 | | Output ( ) A. Exceeds 12 Input Instructions in Series 1 | | 2 | | 3 | | 4 | | 5 | | 6 | | 7 | | | | Storage Bit 8 | | 9 | | 10 | | 11 | | 12 | | 13 | | Storage Bit ( ) ( ) B.
Chapter 4 Introduction to Programming One series condition instruction can be used with a Sequencer Input and an Examine On or Off Shift Bit in series if the output is a block instruction. Up to 4 Examine On or Off Shift Bit instructions can be used in series if the output is not a block instruction. Up to 3 Examine On or Off Shift Bit instructions can be used in series if the output is a block instruction.
Chapter 5 Timer and Counter Instructions 5.0 General Timer and Counter instructions are output instructions internal to the processor. They provide many of the capabilities available with timing relays and solid state timing/counting devices. Usually conditioned by examine instructions, timers and counters keep track of timed intervals or counted events according to the logic continuity of the rung.
Chapter 5 Timer and Counter Instructions The remaining 4 bits in a word (bits 14-17) are not used to form a BCD number. In the accumulated value word, they are used as status bits. In the preset value word, they are not used and are available for internal storage provided data is not transferred to the preset word by a Get/Put transfer. With .01 sec timers these bits are used for internal timing functions and cannot be used for storage.
Chapter 5 Timer and Counter Instructions All three timers differ in the way they set and reset status bits, respond to rung logic continuity and reset the accumulated value. With each timer, the programmer must select one of the following time bases: 1.0 second 0.1 second 0.01 second (10 milliseconds) Bit 16 of the timer accumulated value word reflects the time base. It will go on and off at the selected time base rate acting as a pulse train (Figure 5.2) except for 10 ms timers. 5.1.
Chapter 5 Timer and Counter Instructions Figure 5.3 Timer On Delay, Timing Diagram for a Preset Value of 9 Seconds Accumulated Value and Status Bits are Reset When Input Switch is Opened.
Chapter 5 Timer and Counter Instructions 5.1.2 Timer Off Delay Instruction The Timer Off-Delay instruction (TOF) can be used to turn a device on or off after a timed interval (Figure 5.4). Like the other timer instructions, the TOF instruction counts time-base intervals and stores this count in its accumulated value. The TOF instruction, however, varies from the other instructions in significant ways. The Timer Off-Delay instruction begins to time an interval as soon as its rung conditions go false.
Chapter 5 Timer and Counter Instructions Figure 5.
Chapter 5 Timer and Counter Instructions Figure 5.5 Retentive Timer with Retentive Timer Reset Timing Diagram When Reset Switch is Closed, Timed Bit is Reset. Accumulated Value is Reset and Held at Zero Until Reset Switch is Opened. TRUE Input Switch 113/06 FALSE ON Enable Bit 052/17 OFF Preset Value ACC Value Retained When Rung Condition Goes False ON OFF ON Output Lamp 011/04 OFF ON Reset Switch 113/07 OFF Enable Bit is Reset When Input Switch is Opened.
Chapter 5 Timer and Counter Instructions Unlike the Timer On-Delay instruction, the Retentive Timer instruction retains its accumulated value (Figure 5.5) when any of the following conditions occur: Rung conditions go false Mode select switch is changed to the program position Power outage occurs provided memory backup power is maintained for CMOS RAM memory When rung conditions go true, the enabled bit (bit 17) is set on and the timer starts counting time base intervals.
Chapter 5 Timer and Counter Instructions Bit 14 is the overflow/underflow bit. It is set to one when the AC value of the CTU exceeds 999 or the AC value of the CTD goes below 000. Bit 15 (the Done bit) is set to one when a count has been reached or exceeded, that is, when the AC value is ≥ PR value. Bit 16 is the enabled bit for a CTD instruction. It is set on when rung conditions are true. Bit 17 is the enabled bit for a CTU instruction. It is set on when rung conditions are true.
Chapter 5 Timer and Counter Instructions timer, the CTU instruction continues to increment its accumulated value after the preset value has been reached. If the accumulated value goes above 999, bit 14 is set on to indicate an overflow condition and the CTU continues up-counting from 000. Bit 14 can be examined to cascade counters for counts greater than 999 (Section 5.3). Figure 5.7 Up Counter Diagram and Programming for Preset = 9 Overflow Bit Comes On at 1000th Event. The Counter Does Not Reset.
Chapter 5 Timer and Counter Instructions 5.2.2 Counter Reset Instruction The Counter Reset (CTR) instruction is an output instruction that resets the CTU accumulated value and status bits to zero. The counter operates in the same manner as described for the CTU instruction, with the addition of the reset instruction in rung 3 (Figure 5.8). In this example, the reset push button is pressed after count 11. The next event starts the sequence at count 1.
Chapter 5 Timer and Counter Instructions 5.2.3 Down Counter Instruction The Down-Counter (CTD) instruction subtracts one from its Accumulated Value for each false-to-true transition of its rung conditions (Figure 5.9). Because only the false-to-true transition causes a count to be made, rung conditions must go from true to false and back to true before the next count is registered. Figure 5.
Chapter 5 Timer and Counter Instructions Figure 5.10 Up Down Counter Example 110 | | 00 Up Count Event 110 | | 02 Down Count Event 110 | | 03 Counter Reset Event 046 ( CTU ) PR 220 AC 114 046 ( CTD ) PR 220 AC 114 046 ( CTR ) PR 220 AC 114 NOTE: Bit 14 of the Accumulated Value word is set on when the Accumulated Value either overflows or underflows. When a Down-Counter Preset is set to 000, underflow bit 14 is not set on when the count goes below zero.
Chapter 5 Timer and Counter Instructions 5.3 Cascading Timers or Counters An individual timer or counter can time or count up to 999 intervals or events. By cascading two or more timers or counters, the timing or counting capability within the program can be increased beyond three digits. To cascade timers or counters, each timer or counter is assigned a different word address (Figure 5.12). The status bit of the first timer (bit 15) changes status each time the preset value is reached.
Chapter 5 Timer and Counter Instructions The default word address can be 3, 4 or 5 digits provided the data table is sized accordingly. Unlike bit instructions, the [EXPAND ADDR] key is not required. Instead, the industrial terminal automatically enters a 4- or 5-digit default word address depending on the data table size. When a 4or 5-digit word address is displayed and a 3- or 4-digit word address is required, the programmer must enter leading zeros before the word address. Table 5.
Chapter 5 Timer and Counter Instructions Table 5.B Timer Instructions NOTE: The Timer word address, XXX, is assigned to the timer Accumulated areas of the Data Table. To determine which addresses are valid accumulated areas, the 3rd digit from the right in the word address must be even. The time base, TB, is user selectable and can be 1.0 sec., 0.1 sec., or 0.01 sec. Preset values, YYY, and Accumulated values, ZZZ, can vary from 000 to 999.
Chapter 5 Timer and Counter Instructions Table 5.C Counter Instructions NOTE: The Counter word address, XXX, is assigned to the counter Accumulated areas of the Data Table. To determine which addresses are valid accumulated areas, the 3rd digit from the right in the word address must be even. The word address displayed will be 3, 4, or 5 digits long depending on the Data Table Size. When entering the word address, use a leading zero if necessary.
Chapter 5 Timer and Counter Instructions one millisecond, whichever is greater, when a data highway interface module is connected to the processor. 5.5.2 Program for Determining Scan Time The instruction execution times given in Section 5.6 enable the programmer to estimate scan time for a planned program. The program shown in Figure 5.13 will determine and display the average scan time during program operation: Rung 1 and 2 count the number of scans. At the 1000th scan bit 14 (overflow bit) comes on.
Chapter 5 Timer and Counter Instructions Figure 5.13 Program for Determining Average Scan Time 050 ( CTU ) PR 999 AC 000 1 Branch End Instruction 050 ( CTU ) PR 999 AC 000 2 3 050 |/| 14 4 050 | | 14 5 050 | | 14 051 ( RTR ) PR 999 AC 000 6 050 | | 14 050 ( CTR ) PR 999 AC 000 051 ( RTO ) 0.1 PR 999 AC xxx 051 |G| xxx Store 1 |G| 010 Store 2 (:) xxx Store 3 (:) • xxx 5.
Chapter 5 Timer and Counter Instructions 5.6.2 Word to File, Sequencers, FIFO, Word and Bit Shifts, File Diagnostic, File Search, and Block Transfer Instructions Table 5.E contains longer execution times for more complicated instructions. Note that all of the Table 5.E instruction execution times are affected by file lengths and are longer for larger files. Other factors affecting execution are explained below for specific instructions.
Chapter 5 Timer and Counter Instructions Table 5.D Average Execution Times for Instructions Described In Chapters 3 Through 8 When Instruction is TRUE Execution Time in Microseconds Instruction Name Symbol Examine On1 Examine Off1 Output Energize1 Output Latch1 Output Unlatch1 -| |-| / |-( )-( L )-( U ) - 4 4 4.8 4.8 4.
Chapter 5 Timer and Counter Instructions Table 5.E Average Execution Times for Word To File, Sequencers, Word and Bit Shifts, File Diagnostic, File Search and Block Transfer Instructions Average Execution Time in Microseconds Instruction False True Word To File Move File To Word Move Word To File AND, OR, XOR <1 <1 <1 48 49 75 Sequencer Load Sequencer In Sequencer Out 17 <1 17 60 + (27.8 x # words/step) 58 + (40 x # words/step) 63 + (37 x # words/step) Fifo Unload Fifo Load 16.4 16.
Chapter 5 Timer and Counter Instructions As an example, we will calculate the execution time for File-to-File move in the distributed complete mode for the following conditions: Rate per scan = 256 words operated upon per scan. File length = 542 words 542 words in file = two full 256 word blocks + 30 words. Therefore, use 2 for the number of blocks operated upon per scan and ignore the +30 words. Therefore: Time = 85 + 6.8(256) + 14.4(2) Time = 85 + 1741 + 28.
Chapter 5 Timer and Counter Instructions The execution time, T, in microseconds for the complete mode is: T = 99 + 9.8 (Words operated upon per scan) + 14.4 (Number of 256 word blocks operated upon per scan) Example: What is the execution time to perform a File-to-File AND operation on two files 670 words long? The rate per scan is 256 and the mode is the distributed complete mode. T = 125 + 9.8(256) + 14.4(2) = 125 + 2509 + 28.8 = 2663 T = 2663 microseconds = 2.66 milliseconds.
Chapter 6 Data Manipulation Instructions 6.0 General The data manipulation instructions are used to transfer or compare data that is stored in data table words and bytes. There are six data manipulation instructions: GET –|G|– PUT –(PUT)– LES –|<|– EQU –|=|– GET BYTE –|B|– LIMIT TEST –|L|– The Get and Put instructions are used together to transfer 16 bits of data from one word location in the data table to another word location. Data can be in the form of 3-digit, binary-coded decimal numbers.
Chapter 6 Data Manipulation Instructions The Get Byte and Limit Test instructions compare 3-digit values in octal format using eight bits (one byte) of a data table word (Figure 6.2). This 3-digit value is an octal number ranging from 0008 to 3778. Note that two 3-digit values can be stored in a word: one in the upper byte (bits 10-17) and one in the lower byte (bits 00–07). A Data Manipulation instruction can address any word in the data table, excluding processor work areas. Figure 6.
Chapter 6 Data Manipulation Instructions Figure 6.3 Get and Put Instructions 111 | | 11 130 |G| 238 040 ( PUT ) 238 If the word addressed by a Get instruction already contains data, the lower 12 bits of the data are displayed automatically after the word address is entered. Entry of new data, such as a new BCD value, writes over the data previously stored in the addressed word.
Chapter 6 Data Manipulation Instructions Figure 6.4 Changing a Counter Preset 111 | | 11 130 |G| 238 140 ( PUT ) 238 111 | | 12 NOTE: The Preset of the Counter at Address 040 is at Address 140. 040 ( CTU ) PR 238 AC 047 The lower 12 bits of transferred data are displayed in BCD beneath the Put instruction. Bits 14-17 are not displayed but are transferred. While the rung is true, any change in the data of the Get instruction also changes the data of the Put instruction.
Chapter 6 Data Manipulation Instructions A Get/Les or Get/Equ pair of instructions forms a single condition for logic continuity. Alone or with other conditions, each pair can be used to energize an output device or other output instruction. In all cases, the Get instruction must be programmed before the Les or Equ instruction. If other conditions are also programmed, they should be entered before the Get instruction or after the Les or Equ instruction.
Chapter 6 Data Manipulation Instructions Figure 6.6 Greater Than Comparison 120 | | 02 030 |G| 100 031 |<| YYY 010 ( ) 01 Reference Value When YYY>100, GET/LES comparison is true and 010/01 is energized. Equal To – An equal-to comparison is made with the Get and Equ instructions (Figure 6.7). The Get value is the changing variable and is compared to the reference value of the Equ instruction for an equal-to condition.
Chapter 6 Data Manipulation Instructions Figure 6.8 Less Than or Equal To Comparison 120 | | 04 030 |G| YYY 040 |<| 237 010 ( ) 03 Reference Value 040 |=| 237 When YYY≤237, GET/LES EQU comparison is true and 010/03 is energized. Greater Than or Equal To – This comparison is made using the Get, Les and Equ instructions. The Get value is assigned a reference value. The Les and Equ values are changing values that are compared to the Get value (Figure 6.9).
Chapter 6 Data Manipulation Instructions logic continuity. Condition instructions can be programmed before the Get Byte instruction or after the Limit Test instruction, but not between them (Figure 6.10). Figure 6.10 Get Byte/Limit Test Comparison 120 | | 06 0451 |B| YYY 050 |L| 010 ( ) 05 200 170 Reference Values When 1708≤YYY8≤2008, comparison is true and 010/05 is energized. The Get Byte instruction addresses either the upper or lower byte of a data table word.
Chapter 6 Data Manipulation Instructions The Get Byte instruction addresses either the upper or lower byte of a data table word. A 1 is entered after the word address for an upper byte; a 0 is entered for the lower byte. Figure 6.11 Get Byte-Put Instruction 0451 |B| YYY8 040 ( PUT ) XZZ1 1X is a random value. 6.3 Programming Data Manipulation Instructions ZZ is the transferred byte displayed in hexadecimal.
Chapter 6 Data Manipulation Instructions Table 6.A Data Manipulation Instructions NOTE: Data Manipulation instructions operate upon BCD values and/or 16 bit data in the Data Table. The word address, XXX, is displayed above the instruction; the BCD value or data operated upon, YYY, is displayed beneath it. The BCD value is stored in the lower 12 bits of the word address and can be any value from 000 to 999, except as noted.
Chapter 6 Data Manipulation Instructions 6.4 Arithmetic Instructions The PLC-2/30 processor can be programmed to perform arithmetic operations with two BCD values using a set of arithmetic instructions and can perform conversions from 12-bit binary to BCD and vice versa.
Chapter 6 Data Manipulation Instructions Figure 6.12 Arithmetic Instruction Word BCD Value Holds Arithmetic Result 17 16 15 14 13 12 11 Most Significant Digit 10 07 06 05 Middle Digit 04 03 02 01 00 Least Significant Digit Overflow Bit Set to 1 When Sum Exceeds 999. Underflow Bit Set to 1 When Difference is Negative Number. The conversion instructions are in block format. They don’t require Get instructions.
Chapter 6 Data Manipulation Instructions Figure 6.13 Add Instruction Must be true to allow arithmetic operation 111 | | 11 Result stored at this word address 030 |G| 520 031 |G| 514 032 (+) 1034 Overflow will cause a 1 to be displayed 6.4.2 Subtract Instruction The Subtract instruction tells the processor to subtract the second Get word value from the first Get word value (Figure 6.14). The difference is then stored at the data table word addressed by the Subtract instruction.
Chapter 6 Data Manipulation Instructions 6.4.3 Multiply Instruction The Multiply instruction tells the processor to multiply the two BCD values stored at the Get instruction words. The result is then stored in two data table words addressed by the Multiply instruction (Figure 6.15). For ease of programming, the programmer should choose two consecutive data table words to store the product. If the product is less than 6 digits, leading zeros will appear in the product where there is no value.
Chapter 6 Data Manipulation Instructions Figure 6.16 Divide Instruction Must be true to allow arithmetic operation 111 | | 13 6.5 Programming Arithmetic Instructions 140 |G| 050 141 |G| 025 066 (:) 002 • 067 (:) 000 Arithmetic instructions are entered into memory with the PLC-2/30 Processor in the program mode. When entered, these instructions will be intensified and blinking. They will continue to blink until the word address is entered. Refer to Table 6.B for a summary of these instructions.
Chapter 6 Data Manipulation Instructions Table 6.B Arithmetic Instructions NOTE: Arithmetic instructions operate on BCD values in the Data Table. The word address XXX is displayed above the instruction; the BCD value YYY, which is the result of the arithmetic operation, is displayed beneath it. The BCD value is stored in the lower 12 bits of the word address and they can be any value from 000 to 999. Displayed word addresses will be 3, 4, or 5 digits depending on the Data Table size.
Chapter 6 Data Manipulation Instructions If the BCD value is > 4095, the overflow bit (bit 14 of the binary address) will be set on. The binary number result will be stored in the lower 12 bits (00-13) of a word selected by the user. 6.6.1 Programming a BCD to Binary Conversion Instruction To program a BCD to Binary conversion, press keys [CONVERT] 0. A display represented by Figure 6.17 will appear. Figure 6.
Chapter 6 Data Manipulation Instructions DATA – The BCD number is 004095 (the largest BCD number that can be converted to a 12-bit binary number). BINARY ADDR – Data Table word 025 DATA – The industrial terminal will display 12 ones (1), the binary representation of the decimal number 004095. Figure 6.18 BCD to Binary Conversion Example Rung BCD TO BINARY BCD ADDR: DATA: BINARY ADDR: DATA: 6.
Chapter 6 Data Manipulation Instructions BINARY ADDR – 125 DATA – 111111111111 BCD ADDR – The BCD number is stored in adjacent data table words 200 and 201 DATA – The industrial terminal will display 004095, the BCD equivalent of the binary value for this example. Figure 6.19 Binary to BCD Conversion Format BINARY TO BCD BINARY ADDR: 010 DATA: 000000000000 BCD ADDR: 110- 111 DATA: 000000 010 (OV) 14 Numbers shown are default values. Bold numbers must be replaced by user entered values.
Chapter 6 Data Manipulation Instructions Figure 6.
Chapter 7 Output Override and I/O Update Instructions 7.0 General The user may need programming instructions for certain applications requiring output overrides or I/O updates. They are: Master Control Reset instruction –(MCR)– Zone Control Last State instruction –(ZCL)– Immediate Input instruction –|I|– Immediate Output instruction –(IOT)– 7.
Chapter 7 Output Override and I/O Update Instructions Figure 7.1 MCR and ZCL Zone Programming | | | | | | | | | | ( ZCL ) Start Fence ( ) | | ( ) |/| | | ( ) | | | | ( ) | | |/| |/| | | ( ) ( ZCL ) | | | | | | | | When ZCL zone is false all outputs remain in their last state. | | ( MCR ) Unconditional End Fence Start Fence ( ) | | ( ) |/| | | ( ) | | | | ( ) | | |/| |/| | | When MCR zone is false nonretentive outputs are de energized.
Chapter 7 Output Override and I/O Update Instructions WARNING: MCR or ZCL zones should not be overlapped or nested. Each zone should be separate and complete. Overlapping MCR or ZCL zones may result in unpredictable or hazardous machine operation with possible damage to equipment or personal injury. 7.
Chapter 7 Output Override and I/O Update Instructions Figure 7.2 Scan Sequence I/O Scan Performs I/O Updating (Typically 0.5ms/128 I/O) End of Program Instruction Start of Program Instruction Program Scan, Instructions (typically 6ms/1K) Upon power up, the processor begins the scan sequence with the program scan and then the I/O scan. During the I/O scan, data from the input modules is transferred to the input image table. Data from the output image table is transferred to the output modules.
Chapter 7 Output Override and I/O Update Instructions 7.2.2 Immediate Input Instruction The Immediate Input instruction updates one word of the input image table data in advance of the normal scan sequence (Figure 7.3). The image table word represents one module group in the I/O chassis. The Immediate Input instruction is programmed in the condition area of the ladder diagram rung.
Chapter 7 Output Override and I/O Update Instructions 7.2.3 Immediate Output Instruction The Immediate Output instruction updates one module group with data from one output image table word ahead of the normal scan sequence (Figure 7.4). The Immediate Output instruction is programmed as an output instruction in the ladder diagram rung. This instruction is executed when rung conditions allow logic continuity.
Chapter 7 Output Override and I/O Update Instructions Figure 7.
Chapter 7 Output Override and I/O Update Instructions 7.3 Programming Immediate I/O Instructions The Immediate I/O instructions are programmed with the processor in the program mode. When entered from the industrial terminal, they will be displayed as intensified and blinking with the reverse-video cursor positioned on the first digit of the default word address. The number of digits in the default address can range from 4 to 5 depending on data table size. Refer to Table 7.
Chapter 7 Output Override and I/O Update Instructions 7.4 Remote Fault Zone Programming The remote fault zone programming technique is used to disable parts of or the entire user program when a fault occurs in a remote I/O rack. Remote I/O racks are controlled by the processor via the 1772-SD2 distribution panel and can be located up to 10,000 feet from the panel. Up to two local I/O racks can be used with remote I/O racks in a system (Figure 7.5).
Chapter 7 Output Override and I/O Update Instructions Figure 7.
Chapter 7 Output Override and I/O Update Instructions Fault zones can be programmed around certain parts of the program or the entire program using fault status bits and MCR or ZCL zones. The fault status bits used for remote fault zone programming are located in data table words 1258 and 1268 (Table 7.B). CAUTION: Input modules cannot be located in rack 2, module groups 5 and 6 if words 125 and 126 are used for fault status bits.
Chapter 7 Output Override and I/O Update Instructions Each fault status bit within a group of four corresponds to two consecutive module groups of 32 I/O points (Table 7.B). When a fault occurs in a remote rack, one or more of the four status bits are set on depending on the configuration of the I/O rack. Figure 7.6 Dependent Fault Zone Programming Dependent programming for I/O configuration in Figure 7.
Chapter 7 Output Override and I/O Update Instructions NOTE: If a fault occurs in a local rack, all racks will behave according to their last state switch whether dependent or independent mode has been selected. 7.4.2 Independent Programming Independent fault zone programming is used to zone off independent sections of user program. The programming for each I/O chassis can be contained in separate MCR or ZCL zones or more than one I/O chassis can be contained in a single zone (Figure 7.7).
Chapter 7 Output Override and I/O Update Instructions Figure 7.7 Separate Independent Fault Zone Programming for Individual I/O Chassis Independent programming for I/O configuration in Figure 7.5 When a fault status bit is set on, the MCR or ZCL zone is false and controls all outputs in the zone.
Chapter 7 Output Override and I/O Update Instructions Figure 7.8 Alternate Independent Fault Zone Programming for Individual I/O Chassis Independent programming for I/O configuration in Figure 7.5 When a fault status bit is set on, the MCR or ZCL zone is false and controls all outputs in the zone. The alternate program is enabled when fault status bit 125/00 is set on.
Chapter 7 Output Override and I/O Update Instructions The 1772-SD2 scans remote I/O racks and stores the information in its buffer. The processor, during the I/O scan, updates any local I/O racks and then gets the information from the 1772-SD2 buffer. This information in the buffer may be combination of new and old data depending on where the 1772-SD2 was in its scan when the processor requested the information. To get the information from the 1772-SD2 takes 0.5 ms per remote rack.
Chapter 7 Output Override and I/O Update Instructions Table 7.C Average Execution Times in Microseconds for FILE TO FILE AND, OR, XOR Instructions when Instruction is True Rate Per Scan Dist. Complete Mode Complete Mode 5 10 15 25 50 100 256 512 174 223 272 370 615 1105 2648 5171 148 197 246 344 589 1079 2622 5145 Formula for more exact approximations can be found in Section C.6. Execution Time for incremental mode is 100 microseconds per scan. When FALSE, execution time is 17.
Chapter 8 Peripheral Functions 8.0 General There are several functions that can be performed with a PLC-2/30 and the industrial terminal. Some require the use of a peripheral divide connected to channel C of the industrial terminal. The functions include: Contact histogram Cassette recorder dump and load Data cartridge recorder dump and load Ladder diagram dump Total memory The contact histogram and report generation functions can be monitored by the industrial terminal without a peripheral device 8.
Chapter 8 Peripheral Functions Channel C must be on to receive input from a peripheral device. It is initially on. It can be toggled on/off by pressing [RECORD] 9 (Channel C status display) and pressing 2. Table 8.B Key Sequence for Setting Baud Rate 8.
Chapter 8 Peripheral Functions Table 8.C Contact Histogram Functions Function Mode Key Sequence Description Contact Histogram Continuous RUN RUN/PROGRAM or TEST [SEARCH] [6] [Bit Address] [DISPLAY] Provides a continuous display of the ON/OFF history of the addressed bit in hours, minutes, and seconds. Can obtain a hardcopy printout of contact histogram by connecting a peripheral device to Channel C and selecting proper baud rate before indicated key sequence.
Chapter 8 Peripheral Functions The industrial terminal screen can display up to 11 lines of data at one time. In the continuous mode, the screen will automatically display a new page of data when the screen is full. In the paged mode, 11 lines will fill the screen and stop. Subsequent changes are stored in the buffer until [DISPLAY] is pressed. The data stored in the buffer will then be displayed, one page at a time. To terminate the contact histogram, press [CANCEL COMMAND]. 8.
Chapter 8 Peripheral Functions The cassette load command is accessed by pressing [RECORD] 0 on the PLC-2 family overlay and by pressing either [READ FROM TAPE] or [PLAY] on the cassette recorder. To load the complete memory, rewind the tape to the beginning of the program. As memory is being loaded, the number of data table words and program words will be counted and displayed. When loading is complete, the processor memory content should be verified.
Chapter 8 Peripheral Functions 8.3.5 Displaying and Locating Errors During automatic or program verification, the processor will identify discrepancies between memory content and the content on the cassette tape. By pressing [SEARCH] 9 on the PLC-2 family overlay, the number of program and data table discrepancies found and whether or not the data table was verified will be displayed. Up to 19 discrepancies can be detected.
Chapter 8 Peripheral Functions As memory content is being recorded on tape, the industrial terminal will count the number of user program and data table words and display them as follows: ABCD Program Words EFGH Data Table Words After memory content has been recorded, the tape is automatically rewound and the content verified with the content in memory to be sure that no discrepancies occurred during the recording operation.
Chapter 8 Peripheral Functions 8.4.3 Data Cartridge Verification This command is used to verify user program and messages in processor memory with the content in data cartridge tape, or vice versa. Although the data table size and configuration are checked, the data table content is not verified. With the processor in any mode, verification can be done by pressing the keys [RECORD] [SHIFT] [C] on the industrial terminal keyboard.
Chapter 8 Peripheral Functions The data table printout will be followed by the user program in ladder diagram and block format. The messages will be printed out and identified by number. When the printout is complete, this command is automatically terminated. The total memory dump command can be terminated prior to completion by pressing [ESC] on the peripheral printer or [CANCEL COMMAND] on the PLC-2 family overlay. Figure 8.
Chapter 9 Report Generation 9.0 General The report generation function of the T3 industrial terminal, performed in the PLC-2 mode, can be used to generate messages that contain ASCII and graphic characters, and variable data table information. The messages are stored in the processor’s memory after the END of program statement. We also have a PLC-2 Family Report Generation Module (Cat. No. 1770-RG) which performs the report generation function.
Chapter 9 Report Generation Real-time calendar – you can enter and display the date, and use the date in a message. Date format is month/day/year — July 16, 1984 is 7/16/84.
Chapter 9 Report Generation Figure 9.1 Alphanumeric Keytop Overlays Alphanumeric Keytop Overlay (1770 KAA) Alphanumeric/Graphic Keytop Overlay (1770 KAB) 9.1 Report Generation Commands The report generation function is entered by pressing [RECORD] [DISPLAY] on the PLC-2 Family keytop overlay. There are 6 report generation commands used to enter control words and to store, print, report and delete messages and to display an index of existing messages. These are summarized in Table 9.A.
Chapter 9 Report Generation Table 9.A Report Generation Commands Command Key Sequence Description Enter Report Generation Function [RECORD] [DISPLAY] Puts Industrial Terminal into Report Generation Function. Message Store [M] [S] [,] [message number] [RETURN] Stores message in Processor memory. Use [ESC] to end message. Message Print [M] [P] [,] [message number] [RETURN] Prints message exactly as entered.
Chapter 9 Report Generation the industrial terminal will also display a table (Table 9.B) which shows the message numbers associated with each message control word. Table 9.B Example Message Control Word Message Number Relationship Control Words Message Numbers 200 201 202 203 204 205 206 207 010 017 110 117 210 217 310 317 410 417 510 517 610 617 710 717 NOTE: This table assumes user selected message control words begin at 2008. 9.1.
Chapter 9 Report Generation Table 9.C Address Delimiters Delimiter Format Explanation Message Report Format *XXX* Enter 3 digit word address between delimiters. Displays BCD value at assigned word address. *XXX1* or *XXX0* Enter 3 digit word address and a 1" for upper byte or a 0" for lower byte between delimiters. Displays the octal value at assigned byte address. *XXXXX* Enter 5 digit bit address between delimiters. Displays the ON or OFF status of the assigned bit address.
Chapter 9 Report Generation The message print command is self-terminating. [ESC] or [CANCEL COMMAND] can be used to return to ladder diagram display. 9.1.4 Message Report - MR Accessible in any mode, the message report command is used to print a message with the current data table value or bit status that corresponds to an address between the delimiters. This command is accessed by pressing [M] [R] [,] [message number] [RETURN]. In the example, the message report command would give the following: (e.g.
Chapter 9 Report Generation The T3 industrial terminal screen size is an 80 x 24 format: 80 columns across by 24 lines down. An example message using graphic and alphanumeric characters is shown in Figure 9.2. The control code, [CTRL] [P] [Column #] [;] [Line #] [A], should be used for cursor positioning to conserve memory when possible. For example, [CTRL] [P] [3] [9] [;] [9] [A] uses 3 words of memory, storing CRTL P in one byte and each remaining character in one byte each.
Chapter 9 Report Generation Table 9.D Alphanumeric/Graphic Keytop Definitions Key Function [LINE FEED] Moves the cursor down one line in the same column. [RETURN] Returns the cursor to the beginning of the next line. [RUB OUT] Deletes the last character or control code that was entered. [REPT LOCK] Allows the next character that is pressed to be repeated continuously until [REPT LOCK] is pressed again. [SHIFT] Allows the next key pressed to be a shift character.
Chapter 9 Report Generation Table 9.E Industrial Terminal Control Codes Control Code Key Sequence Function [CTRL] [P] [Column #] [;] [Line #] [A] Positions the cursor at the specified column and line number. [CTRL] [P] [A] will position the cursor at the top left corner of the screen. [CTRL] [P] [F] Moves the cursor one space to the right. [CTRL] [P] [U] Moves the cursor one line up in the same column. [CTRL] [P] [5] [C] Turns cursor ON. [CTRL] [P] [4] [C] Turns cursor OFF.
Chapter 9 Report Generation Table 9.F ASCII Control Codes Control Code1 Display2 ASCII Mnemonic Name CTRL 03 CTRL A3 CTRL B3 CTRL C3 CTRL D CTRL E CTRL F CTRL G CTRL H CTRL I CTRL J CTRL K CTRL L CTRL M CTRL N CTRL O CTRL P CTRL Q CTRL R CTRL S CTRL T CTRL U CTRL V CTRL W CTRL X CTRL Y CTRL Z ESCAPE CTRL , CTRL CTRL .
Chapter 9 Report Generation 9.3 Automatic Report Generation Messages can be printed through program control automatically be energizing specific message request bits using output latch and output unlatch instructions. Automatic report generation can be accessed if the keyswitch is in the TEST, RUN, or RUN/PROGRAM position by pressing [SEARCH] 40 or by pressing [M] [R] [RETURN].
Chapter 9 Report Generation 9.3.1 Messages 1 6 Messages 1-6 use bits 10-15 of word 027 as message request bits. All other messages use a user-defined file of message request bits for control. These two categories will be discussed separately. The upper byte of word 027 is used to control messages 1-6. Bit 027/10 is the request bit for message number 1; bit 027/11 is the request bit for message number 2 and so on.
Chapter 9 Report Generation Figure 9.5 Message Request Bit Done Bit Relationship Message Request Bits 17 Message Done Bits 10 07 00 Message Control Word The message print command is valid for message 0. It will print out the message control word addresses such as tabular form shown in Table 9.B. If the location of the message control file is to be changed or if message 0 is no longer needed, it can be deleted with the message delete command and re-entered at any time.
Chapter 9 Report Generation Figure 9.
Chapter 10 Block Transfer 10.0 General Block transfer is a combination of an instruction and support rungs used to transfer up to 64 16-bit words of data in one scan from I/O modules to/from the data table. It is used with intelligent I/O modules such as the analog, PID, servo positioning, stepper positioning, ASCII, thermocouple, or encoder/counter modules which have this capability. Block transfer can be compared to single transfer programming in which only one word of data is transferred per scan.
Chapter 10 Block Transfer Figure 10.1 Module Position Image Table Byte Relationship Data Table I/O Rack 17 Output Image Table Word, Lower Byte Bit Numbers 10 07 00 010 Output Image Table ÉÉÉÉÉÉ ÉÉÉÉÉÉ 012 Block Transfer Module Control Byte 017 Input Image Table Word, Lower Byte ÉÉÉÉÉÉ ÉÉÉÉÉÉ 110 Input Image Table 112 Status Byte 117 Lower Upper Slot Slot The lower byte of the I/O image table words are used when the module is in the lower slot and vice versa.
Chapter 10 Block Transfer Figure 10.2 Block Transfer Diagram Transfer is made in I/O Scan Output Scan Input Scan Request is made in Program Scan Once the module address is found, the processor locates the address of the file to which (or from which) the data will be transferred. The file address is stored in BCD at an address 1008 above the address containing the module address.
Chapter 10 Block Transfer 10.2 Block Transfer Instructions The format of a block transfer read and a block transfer write instruction with default values is shown in Figure 10.3. Figure 10.3 Block Transfer Format BLOCK XFER READ DATA ADDR 030 MODULE ADDR 100 BLOCK LENGTH 01 FILE 110- 110 BLOCK XFER WRITE 030 DATA ADDR MODULE ADDR 100 BLOCK LENGTH 01 FILE 110- 110 010 (EN) 07 110 (DN) 07 010 (EN) 06 110 (DN) 06 Numbers shown are default values. Bold numbers must be replaced by user entered values.
Chapter 10 Block Transfer Table 10.B The First Available Address in Timer/Counter Area of Data Table # I/O Racks First Available Address in Timer/Counter Area 1 2 3 4 5 6 7 020 030 040 050 060 070 200 The module address is stored in BCD by r=rack, g=module group and s=slot number. When block transfer is performed, the processor searches the timer/counter accumulated area of the data table for a match of the module address. 10.2.
Chapter 10 Block Transfer 10.2.4 Enable Bit and Done Bit The read and write bits are the enable bits for block transfer modules. Either one (or both for a bidirectional transfer) is set on in the program scan when the rung containing the block transfer instruction is true. The done bit is set on in the I/O scan that the words are transferred, provided that the transfer was initiated and successfully completed. The done bit remains on for only one scan.
Chapter 10 Block Transfer Figure 10.4 Data Table Locations for a Block Transfer Read Instruction 010 Data Table R Output Image Table 1 Block Length Code 012 017 027 1 Timer/ Counter Accumulated Area 2 1 030 Data address contains module address in BCD. 060 First File Word 067 Last File Word Block Transfer Data 110 R Input Image Table Output image table byte contains read enable bit and block length in binary code. 1 112 Input image table byte contains done bit.
Chapter 10 Block Transfer During the program scan when input switch 113/02 is closed, the instruction is enabled and read bit 012/17 is set to 1. In the next scan of the output image table, the upper byte data of word address 012 is sent to the module. The module responds that it is ready for transfer. The processor interrupts the output image table scan and starts searching the timer/counter accumulated area of the data table.
Chapter 10 Block Transfer WARNING: When programming multiple writes (or reads) to the same module, it is possible that a desired transfer will not take place or the number of words transferred will not be the number intended. Invalid data could be sent to an analog output device (or could be operated upon in subsequent scans) resulting in unpredictable and/or hazardous machine operation. Refer to the module user’s manual for any information unique to that module.
Chapter 10 Block Transfer Figure 10.
Chapter 10 Block Transfer 10.7 Defining the Block Transfer Data Address Area When the block transfer instructions are used, the first word and consecutive words of the timer/counter accumulated area of the data table must be reserved for block transfer data addresses. Block transfer data addresses should be separated from the addresses of timer and counter instructions by inserting a boundary.
Chapter 10 Block Transfer 10.8 Buffering Data The purpose of block transfer data buffering is to allow the data to be validated before it can be used. Data that is read from the block transfer module and transferred to data table locations must be buffered. Data that is written to the module need not be buffered because block transfer modules perform this function internally. Transferred data is buffered to ensure that both the transfer and the data are valid.
Chapter 10 Block Transfer Figure 10.7 Buffering Data R 1 Block Length Code 0 4 1 0 014 Data in the buffer file 050 052 will be moved to 150 152 when: 030 050 Block Transfer Data (Buffer) A. Done Bit 114/07 is set (valid transfer) B.
Chapter 10 Block Transfer 10.9 Bidirectional Block Transfer 2. Block Transfer will be enabled during the program scan. The transfer will be performed during an interruption of the next I/O scan. Data from the module will be loaded into words 050-052. When block transfer is complete, done bit 114/07 is set in the input image table byte. This indicates that the block transfer was successfully performed. The processor then continues with the I/O scan and program scan. 3.
Chapter 10 Block Transfer The data table locations and block instructions for this example are shown in Figure 10.8.
Chapter 10 Block Transfer Figure 10.8 Data Table Locations for Bidirectional Block Transfer 010 Data Table R W 1 Block Length Code 1 013 Output Image Table Low Byte R W 1 1 1 3 0 040 1 3 0 041 060 5 words of data table are to be written to the bidirectional block transfer modul starting form word 0508. 070 5 words of data are to be read from the module and loaded into the data table starting at word 0708.
Chapter 10 Block Transfer 10.9.2 Data Address and Module Address The module address is stored in BCD in the data address of the read and write instructions. In this example, the module address is 130: rack 1, module group 3, slot 0. Two data addresses must be used. In this example, they are 040 and 041. Both contain the module address. For bidirectional operation, each data address word also contains an enable bit; bit 16 for a write operation (in 041) and bit 17 for a read operation (in 040).
Chapter 10 Block Transfer 10.9.5 Programming Considerations The programming of a bidirectional block transfer module depends on whether the read and write instruction block lengths are equal or unequal. Equal Block Lengths When the block lengths are set equal or when the default block length is specified by the programmer, the following considerations are applicable: Read and write instructions could and should be enabled in the same scan (separate but equal input conditions).
Chapter 11 Jump Instructions and Subroutine Programming 11.0 General The Jump instruction and subroutine programming allow programming flexibility and efficiency. Four instructions are used to implement program jumps and subroutines: Jump – JMP Label – LBL Jump to Subroutine – JSR Return – RET The Jump and Label instructions allow portions of a program to be selectively jumped over in order to reduce scan time.
Chapter 11 Jump Instructions and Subroutine Programming Figure 11.1 JUMP Format XX ( JMP ) | | XX = Octal Identification Number Figure 11.2 JUMP to LABEL Operation 117 | | 10 117 |/| 11 016 ( ) 01 117 | | 13 07 ( JMP ) 200 |/| 15 200 ( TON ) 0.1 PR 999 AC 000 Jumped sections of programs are not scanned. 117 | | 10 07 LBL 200 |/| 15 117 -| |When is true, 13 program execution jumps to label 07. 016 ( ) 13 117 | | 17 015 ( ) 02 200 ( TON ) 0.
Chapter 11 Jump Instructions and Subroutine Programming Instruction overview: Output instruction Can jump 1 or more times to the label with the same identification number. Uses 1 word of memory Has 2 digit octal identification number Caution is advised when jumping over timers or counters. Causes of run-time errors: NOTE: Do not misuse the Jump instruction. Misuse generally results in a run-time error which causes the processor to fault.
Chapter 11 Jump Instructions and Subroutine Programming Table 11.A Jump/Subroutine Programming Key Symbol Instruction Name 1770 T3 Display Description SBR T.END SUBROUTINE AREA SUBROUTINE AREA Establishes the boundary between Main Program and Subroutine Area. Subroutine Area is not scanned unless directed to do so by a JSR instruction. LBL -(JMP)- LABEL XX -LBL- This condition instruction is the target destination for JMP and JSR instructions.
Chapter 11 Jump Instructions and Subroutine Programming Figure 11.
Chapter 11 Jump Instructions and Subroutine Programming Figure 11.5 Multiple JUMPS to LABEL in Subroutine Area and Multiple Return Paths to Main Program Main Program | | A 03 ( JSR ) |/| | | ( ) a | | 03 ( JSR ) b ( ) c 03 LBL Subroutine Area | | ( ) | | B | | | | C | | 03 ( JSR ) (Subroutine) ( RET ) | | | | ( ) 11.2 Label Instruction The Label instruction shown in Figure 11.6 is the target destination for both the Jump and Jump to Subroutine instructions.
Chapter 11 Jump Instructions and Subroutine Programming The Label instruction is always logically true. It should be programmed as the first condition instruction in the rung. If conditions precede a Label instruction in a rung, they will be ignored by the processor during a jump operation.
Chapter 11 Jump Instructions and Subroutine Programming enables a subroutine to call itself or loop. This will be explained in Section 11.3.3. Instruction overview: Output instruction Must always jump from main program into subroutine area or from one subroutine to another Can jump 1 or more times to the label with the same identification number Uses 1 word of memory Figure 11.
Chapter 11 Jump Instructions and Subroutine Programming Figure 11.8 JUMP TO SUBROUTINE LABEL Operation 117 | | 10 117 |/| 11 016 ( ) 01 117 | | 13 06 ( JSR ) 117 | | 15 200 ( TON ) 0.1 PR 999 AC 000 117 | | 10 117 -| |When is true, 13 program execution jumps to subroutine label 06. 016 ( ) 13 116 | | 12 116 | | 14 06 LBL 114 | | 16 012 | | 14 046 ( ) 12 036 ( ) 06 ( RET ) At the end of subroutine program, execution returns to user program at next instruction after subroutine jump.
Chapter 11 Jump Instructions and Subroutine Programming 11.3.1 Subroutine Area The area reserved for subroutines is located in memory between the main program and the message store areas. Its boundary is displayed as subroutine area, and serves as the end of program statement for the main program. Subroutines are not scanned by the processor unless directed to do so by the Jump to Subroutine instruction.
Chapter 11 Jump Instructions and Subroutine Programming Figure 11.9 Representative Subroutine Area Main Program | | The label is the first instruction in each subroutine. XX LBL | | |/| ( ) Subroutine Area | | |/| ( ) Subroutine boundary serves as end statement for main program. (Subroutine #1) ( RET ) XX LBL | | ( ) (Subroutine #2) ( RET ) XX LBL Up to sixty four (64) subroutines can be programmed if no jumps are programmed. 11.3.
Chapter 11 Jump Instructions and Subroutine Programming 11.3.3 Recursive Subroutine (Looping) Calls A subroutine can loop or call itself (Figure 11.10b). If this procedure is used, it is recommended that a scan counter be used to ensure that a maximum of 9 JSR’s (including the original one in the main program) is not exceeded. If 9 JSR’s are exceeded, it would cause a processor fault. For example, if the looping occurs in Level-1 subroutine, the counter preset value should be a maximum of 009.
Chapter 11 Jump Instructions and Subroutine Programming Figure 11.10 (a) Three Levels of Nested Subroutines (b) A Subroutine Can Call Itself or Loop (A.) Subroutine Area Subroutine Level 1 Main Program 01 ( JSR ) a Subroutine Level 2 01 LBL Subroutine Level 3 02 LBL 03 LBL b c 02 ( JSR ) 03 ( JSR ) ( RET ) ( RET ) f e (B.
Chapter 11 Jump Instructions and Subroutine Programming 11.4 Return Instruction The Return instruction is an output instruction (Figure 11.11). It is used only in the subroutine area to terminate a subroutine and to return program execution to the main program (Figure 11.8) or, in the case of nested subroutines, to return program execution to the preceding subroutine (Figure 11.11). It returns program execution to the instruction immediately following the JSR that initiated the subroutine.
Chapter 12 Data Transfer File Instructions 12.0 General This chapter introduces concepts in two major areas: Files Data monitor mode Later chapters of this manual are written with the assumption that the concepts and terms covered in this chapter have been thoroughly learned. In particular, do not proceed into Chapters 13-17, File, Sequencer, and Shift Register instructions, until this chapter is completely understood. 12.
Chapter 12 Data Transfer File Instructions Figure 12.1 File Structure Counter Addr: 200 Starting Address of File: 600 File Length - 012 = Preset Value Position = 005 = Accumulated Value Position Word Address 001 005 Current Word Being Operated Upon (5th Word = Word 6048) 012 12.1.2 File Planning 600 ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ 604 File Length = 12 Words 613 Although files can be located anywhere within the data table, they usually should be located after the last timer/counter preset area.
Chapter 12 Data Transfer File Instructions Figure 12.2 File Instruction Format FILE-TO-FILE MOVE COUNTER ADDR: POSITION: FILE LENGTH: FILE A: 110FILE R: 110RATE PER SCAN: 030 001 001 110 110 001 030 (EN) 17 030 (DN) 15 Numbers shown are default values. Bold numbers must be replaced by user entered values. The number of default address digits initially displayed 3, 4, or 5 will depend on the size of the data table. Initially displayed default values are governed by the I/O rack configuration.
Chapter 12 Data Transfer File Instructions Externally Indexed Counter When the counter is externally indexed, the accumulated value must be positioned to point to a word in the file by instructions in the user program. The counter can be indexed randomly by using a Get/Put transfer or sequentially by using another counter. In either case, the other instructions are addressed to the accumulated value of the file instruction counter.
Chapter 12 Data Transfer File Instructions Figure 12.4 Example of an Internally Indexed File Instruction FILE-TO-FILE MOVE COUNTER ADDR: POSITION: FILE LENGTH: FILE A: 512FILE R: 562RATE PER SCAN: 214 001 014 527 577 014 214 (EN) 17 214 (DN) 15 Notice that another term has been added to the instruction block: rate per scan. It defines the number of words in the file operated upon during one scan. Its value is user-chosen according to how the file operation is to take place.
Chapter 12 Data Transfer File Instructions Figure 12.5 Complete Mode Operation Data Table 512 One Scan Rate Per Scan = 14 = File Length. Entire file is operated upon in 1 scan. 14 Word File 517 520 Operation goes to completion after a single false to true transition of the rung condition. 527 The operation of the status bits for the complete mode is shown in Figure 12.6. The instruction is enabled by the false-to-true transition of the rung condition.
Chapter 12 Data Transfer File Instructions Figure 12.6 Status Bits for Complete Mode 1 Scan Rung Condition Enable Bit (17) Done Bit (15) Instruction Operation A = Status bits are reset to zero and counter is reset to word 1. Distributed Complete Mode In cases where is is not necessary that the file operation be completed in one program scan, it may be advantageous to distribute the file operation over several program scans. This is to avoid overextending the scan time of any one program scan.
Chapter 12 Data Transfer File Instructions Figure 12.7 Distributed Complete Mode Operation Data Table 512 Scan #1 516 517 Scan #2 523 524 Scan #3 5 Words Scan #1 5 Words Scan #2 Remaining 4 Words Scan #3 527 Rates Per Scan = 005 File is operated upon over 3 scans. Operation goes to completion after a single false to true transition of the rung condition. The File instruction, once enabled, remains enabled for the number of scans necessary to complete the operation.
Chapter 12 Data Transfer File Instructions Figure 12.8 Status Bits for Distributed Complete Mode More than 1 Scan Rung Condition Enable Bit (17) Done Bit (15) A Instruction Operation A = Status bits are reset to zero and counter is reset to word 1. a) Rung is True at completion. More than 1 Scan Rung Condition Enable Bit (17) Done Bit (15) A Instruction Operation A = Done bit is reset to zero and counter is reset to word 1. b) Rung is False at completion.
Chapter 12 Data Transfer File Instructions Incremental Mode The incremental mode allows the file to be operated upon one word per rung transition. Each time the rung containing the instruction goes from false to true, the instruction operates on the word pointed to by the counter accumulated value, and then increments to the next word. The operation of a file instruction in the incremental mode is shown in Figure 12.9. In this mode, the rate per scan is set equal to zero. Figure 12.
Chapter 12 Data Transfer File Instructions scans equal to the file length. In the incremental mode (r = 0), the operation must be enabled by a separate false-true transition for each word in the file. The operation of the status bits in the incremental mode is illustrated in Figure 12.10. The enable bit is on if the rung is true. After the last word in the file has been operated upon, the done bit comes on.
Chapter 12 Data Transfer File Instructions entered. Default values are presented in the instruction block. A character cursor will indicate where instruction parameters are to be entered. The programming and operation of the block instructions are covered in detail in the section specifically assigned to each instruction. 12 12 12.1.5 File Instruction Run Time Error If the counter accumulated value exceeds its preset value, the instruction counter will be indexed outside the file.
Chapter 12 Data Transfer File Instructions Figure 12.11 FILE TO FILE MOVE Operation Move 10 word file (starting at location 410) to 10 word file (starting at location 474).
Chapter 12 Data Transfer File Instructions 12.2.1 Programming File to File Move Instructions WARNING: The counter address for the File-to-File move instruction should be reserved for that instruction. Do not manipulate the counter accumulated or preset values. Inadvertent changes to these values could result in unpredictable or hazardous machine operation or a run-time error. Damage to equipment and/or personal injury could result. To program a File-to-File move instruction, press keys [FILE] 10.
Chapter 12 Data Transfer File Instructions COUNTER ADDR – 200 POSITION (set by instruction) – 001 FILE LENGTH – 010 FILE A – starts at 410 and ends at 421 FILE R – starts at 474 and ends at 505 RATE PER SCAN – 010 steps of the files are operated upon each scan (complete mode) The procedure for using the data monitor to enter and/or monitor files is presented in Section 12.5. Figure 12.
Chapter 12 Data Transfer File Instructions Figure 12.14 FILE TO WORD MOVE Operation Words within file A (starting at location 474) are moved to word 400. Counter 200: PR = 010 AC = 005 474 Word W 400 500 File A (10 words) Value at 5th location in file (word 500) will be moved to word 400. 505 12.3.
Chapter 12 Data Transfer File Instructions Figure 12.15 FILE TO WORD MOVE Format FILE-TO-WORD MOVE COUNTER ADDR: POSITION: FILE LENGTH: FILE A: 110WORD ADDRESS: 030 001 001 110 010 030 (DN) 15 Numbers shown are default values. Bold numbers must be replaced by user entered values. The number of default address digits initially displayed 3, 4, or 5 will depend on the size of the data table. Initially displayed default values are governed by the I/O rack configuration.
Chapter 12 Data Transfer File Instructions Figure 12.16 FILE TO WORD MOVE Example Rung FILE-TO-WORD MOVE COUNTER ADDR: POSITION: FILE LENGTH: FILE A: 474WORD ADDRESS: 12.4 Word to File Move 200 005 010 505 400 This output instruction transfers a duplicate of the value in a specified data table word W (Figure 12.17) into a word in file R that is pointed to by the counter accumulated value.
Chapter 12 Data Transfer File Instructions Figure 12.17 WORD TO FILE MOVE Operation Value in word 500 moved into indexed position within file R (starting at location 474). Counter 050: PR = 010 AC = 005 474 Word W 500 400 File R (10 words) Value at word 400 will be moved into 5th location of file, specifically data table word 500. 505 12.4.
Chapter 12 Data Transfer File Instructions Figure 12.18 WORD TO FILE MOVE Format WORD-TO-FILE MOVE COUNTER ADDR: POSITION: FILE LENGTH: WORD ADDRESS: FILE R: 110- 030 001 001 010 110 030 (DN) 15 Numbers shown are default values. Bold numbers must be replaced by user entered values. The number of default address digits initially displayed 3, 4, or 5 will depend on the size of the data table. Initially displayed default values are governed by the I/O rack configuration.
Chapter 12 Data Transfer File Instructions Figure 12.19 WORD TO FILE MOVE Example Rung WORD-TO-FILE MOVE COUNTER ADDR: POSITION: FILE LENGTH: WORD ADDRESS: FILE R: 474- 050 05 010 400 505 050 (DN) 15 12.5 Data Monitor Mode The data monitor mode can be used to monitor, load and edit data. Each file instruction has two corresponding data monitor displays. One displays file data in binary and the other displays file data in hexadecimal representation.
Chapter 12 Data Transfer File Instructions Table 12.B Accessing the Display1 Key Sequence Explanation [DISPLAY] X Accesses data monitor format. [DISPLAY] X [RECORD]2 Prints first 20 lines of the data monitor. [DISPLAY] X [HELP]2 Accesses the ASCII/Hexadecimal conversion table. [DISPLAY] X [HELP] [RECORD]2 Prints the ASCII/Hexadecimal conversion table.
Chapter 12 Data Transfer File Instructions Figure 12.
Chapter 12 Data Transfer File Instructions 12.5.2 Data Monitor Display Data monitor displays, although unique for each File instruction, have common characteristics including a header section, a file section and a command buffer. Header The header is located at the top of the screen and contains information pertinent to its corresponding File instruction, such as: counter address, file addresses, current position value and length value.
Chapter 12 Data Transfer File Instructions The command buffer is always displayed when the processor is in program mode. When in run/program mode, the command buffer will not be displayed unless the on-line data change feature is being used. 12.5.3 Cursor Controls The field cursor and digit cursor are used together to enter or change file data. Field Cursor The field cursor initially appears in the top left position of the file section.
Chapter 12 Data Transfer File Instructions Digit Cursor The digit cursor initially appears in the left-most position in the command buffer. It can be moved to the right or left within the command buffer by pressing the [→] or [←] cursor command keys, respectively. It will not respond to a command to move outside the buffer area. Whenever the command buffer is displayed, the digit cursor will always be reverse video. The digit cursor commands are summarized in Table 12.D. Table 12.
Chapter 12 Data Transfer File Instructions Table 12.E Paging and Specified Paging Key Sequence Explanation [SHIFT] [↓] Displays the next full page of data. [SHIFT] [↑] Displays the previous full page of data. [DISPLAY] [X] [X] [X] Specified paging presents a page beginning at the desired file word XXX. The Field Cursor moves to word XXX.
Chapter 12 Data Transfer File Instructions Table 12.F Data Entry Commands Key Sequence Explanation [D] [D] [D] [D]1 Data is entered or changed in the Command Buffer. [INSERT] Command Buffer data is loaded into Processor memory and placed into the file word located by the Field Cursor. [CANCEL COMMAND] Terminates Data Monitor Mode and returns display to Ladder Diagram. If in On Line Data Change, [CANCEL COMMAND] will terminate On Line Data Change.
Chapter 13 Shift Register Instructions 13.0 General The file shift instructions are: Shift File Up Shift File Down FIFO Load FIFO Unload The first two output instructions are used to construct synchronous word shift registers from 1 to 999 words long (Figure 13.1). Upon false-true transition of rung decision, the data from input word will be shifted into the file, and the data in the last/first word of the file will be shifted up/down into the output word. Figure 13.
Chapter 13 Shift Register Instructions The FIFO Load and FIFO Unload output instructions that are always used together to construct an asynchronous word shift register (Figure 13.2) up to 999 words long. Upon false-true transition of rung decision, the contents of the input word will be transferred into the stack (FIFO Load); or the contents of the word designated by the unload pointer will be transferred to the output word (FIFO Unload).
Chapter 13 Shift Register Instructions input word of data and to shift out one word of data to the output word. The output word data should NOT be considered valid until the bit is set. Instruction overview: Output instruction Key sequence: [SHIFT REG] 10 Counter manipulated by instruction Can operate in distributed complete or complete modes Requires 6 words of user program 13.1.
Chapter 13 Shift Register Instructions Figure 13.3 SHIFT FILE UP Format SHIFT FILE UP COUNTER ADDR: FILE LENGTH: FILE: 110INPUT ADDR: OUTPUT ADDR: RATE PER SCAN: 030 001 110 010 010 001 030 (EN) 17 030 (DN) 15 Numbers shown are default values. Bold numbers must be replaced by user entered values. The number of default address digits initially displayed 3, 4, or 5 will depend on the size of the data table. Initially displayed default values are governed by the I/O rack configuration.
Chapter 13 Shift Register Instructions Figure 13.4 SHIFT FILE UP Example Rung SHIFT FILE UP COUNTER ADDR: FILE LENGTH: FILE: 400INPUT ADDR: OUTPUT ADDR: RATE PER SCAN: 13.2 Shift File Down 200 064 477 120 500 064 200 (EN) 17 200 (DN) 15 This instruction can be used as a synchronous word shift register. When the rung goes true, the data from a specified input word is shifted into the last word file (Figure 13.
Chapter 13 Shift Register Instructions To program a Shift File Down instruction press keys [SHIFT] [REG] 11. The format that appears and the technique for insertion of numbers, will be identical to that for Shift File Up (Figures 13.3 and 13.4) except that the title will read Shift File Down. The procedure for using the data monitor mode to monitor/edit file data is presented in Chapter 12. 13.
Chapter 13 Shift Register Instructions Figure 13.5 Format for FIFO LOAD and FIFO UNLOAD Instructions FIFO UNLOAD 030 COUNTER ADDR: FIFO SIZE: 001 NUMBER IN FILE: 000 FILE: 110- 110 INPUT ADDR: 010 INPUT DATA: 0000 030 (EN) 17 030 (FL) 15 030 (EM) 14 Numbers shown are default values. Bold numbers must be replaced by user entered values. The number of default address digits initially displayed 3, 4, or 5 will depend on the size of the data table.
Chapter 13 Shift Register Instructions 13.3.1 Programming FIFO Load and FIFO Unload Instruction WARNING: The counter address specified for FIFO Load and FIFO Unload instructions should be reserved for these instructions. Do not manipulate the counter accumulated or preset values. Inadvertent changes to these values could result in unpredictable or hazardous machine operation or run-time error. Damage to equipment and/or personal injury could result. To program FIFO load press keys [SHIFT REG] 14.
Chapter 13 Shift Register Instructions Figure 13.6 FIFO LOAD and FIFO UNLOAD Example Rung (A.) FIFO UNLOAD 200 COUNTER ADDR: FIFO SIZE: 064 NUMBER IN FILE: 000 FILE: 400- 477 INPUT ADDR: 130 INPUT DATA: 0000 (B.
Chapter 14 Bit Shifts 14.0 General The Bit Shift instructions are: Bit Shift Left Bit Shift Right Examine Off Shift Bit Examine On Shift Bit Set Shift Bit Reset Shift Bit The Bit Shift Left and Bit Shift Right instructions are output instructions used to construct and manipulate a synchronous bit shift register from 1 to 999 bits in length. Figure 14.1 shows a 128-bit shift register. Upon false-true transition of rung decision the contents of the shift register moves one bit to the right or left.
Chapter 14 Bit Shifts Figure 14.1 BIT SHIFT LEFT/RIGHT Operation (A.) 128 Bit Shift Register (Starting at Location 400) Input Bit A 17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00 L 16 15 14 13 12 11 10 1 400 17 401 33 402 49 403 67 66 65 L 404 81 405 97 406 113 407 9 8 7 6 5 4 3 2 L L 32 L L L L L L 48 64 80 L 96 L L L L 112 Output Bit A 128 127 123 Bit one of Bit Shift Register L (B.
Chapter 14 Bit Shifts Upon false-true transition, bit A from a particular input word will be shifted into the first bit of the bit shift register. Bit 1 will move to the left and displace bit 2. Bit 2 will displace bit 3, etc. Each bit displaces the one to its left until the last bit in the word (bit 16) is reached. Bit 16 then replaces bit 00 in the next word. This bumping procedure continues throughout the file until the last bit is ejected from the stack into bit B in a particular output word.
Chapter 14 Bit Shifts Figure 14.2 BIT SHIFT LEFT Format BIT SHIFT SHIFT COUNTER ADDR: 030 NUMBER OF BITS: 001 FILE: 110- 110 INPUT: 010/00 OUTPUT: 010/00 030 (EN) 17 030 (DN) 15 Numbers shown are default values. Bold numbers must be replaced by user entered values. The number of default address digits initially displayed 3, 4, or 5 will depend on the size of the data table. Initially displayed default values are governed by the I/O rack configuration.
Chapter 14 Bit Shifts Figure 14.3 BIT SHIFT LEFT Example Rung BIT SHIFT SHIFT COUNTER ADDR: 200 NUMBER OF BITS: 128 FILE: 400- 407 INPUT: 130/17 OUTPUT: 420/00 14.2 Bit Shift Right 200 (EN) 17 200 (DN) 15 The Bit Shift Right output instruction constructs a synchronous bit shift register from 1 to 999 bits in length . Figure 14.1B shows a 128-bit register starting at words 400 and 407.
Chapter 14 Bit Shifts 14.2.1 Programming Bit Shift Right Instruction WARNING: The counter address specified for the Bit Shift Right instruction should be reserved for that instruction. Do not manipulate the counter preset or accumulated values. Inadvertent change to these values could result in hazardous or unpredictable machine operation or a run-time error. Damage to equipment and/or personal injury could result. To program a Bit Shift instruction press [SHIFT REG] 13.
Chapter 14 Bit Shifts Figure 14.4 EXAMINE OFF SHIFT BIT Format EXAMINE OFF SHIFT BIT FILE: BIT NO.: 110 001 Numbers shown are default values. Bold numbers must be replaced by user entered values. The number of default address digits initially displayed 3, 4, or 5 will depend on the size of the data table. Initially displayed default values are governed by the I/O rack configuration. FILE : Starting address of the file (file of bit shift instruction).
Chapter 14 Bit Shifts 14.4 Examine On Shift Bit This condition instruction examines a user specified bit in a bit shift register, such as shown in Figure 14.1, for an on or 1 condition. The instruction can be used alone or in conjunction with other input instructions to affect the rung decision. Instruction overview: Input instruction Key sequence: [SHIFT REG] 19 3 words of users program required 14.4.
Chapter 14 Bit Shifts Figure 14.7 EXAMINE ON SHIFT BIT Example Rung EXAMINE ON SHIFT BIT FILE: BIT NO.: 14.5 Set Shift Bit 400 067 The Set Shift Bit output instruction sets a specified bit in a bit shift register such as that shown in Figure 14.8. The user specifies the bit number of the bit to be set and the starting address of the file. The instruction executes upon a true-rung condition. NOTE: If file is shifted, new data in the same bit position will be set if set shift bit rung is still true.
Chapter 14 Bit Shifts Figure 14.8 SET SHIFT BIT Format SET SHIFT BIT FILE: BIT NO.: 110 001 Numbers shown are default values. Bold numbers must be replaced by user entered values. The number of default address digits initially displayed 3, 4, or 5 will depend on the size of the data table. Initially displayed default values are governed by the I/O rack configuration. FILE : Starting address of the file (file of bit shift instruction). BIT NUMBER : Decimal number of the bit to be set (1 999).
Chapter 14 Bit Shifts Instruction overview: Output instruction 3 words of users program required Key sequence: [SHIFT REG] 17 14.6.1 Programming Reset Shift Bit Instruction To program a Reset Shift Bit instruction press [SHIFT REG] 17. A display represented by Figure 14.10 will appear. Figure 14.10 RESET SHIFT BIT Format RESET SHIFT BIT FILE: BIT NO.: 110 001 Numbers shown are default values. Bold numbers must be replaced by user entered values.
Chapter 15 Sequencer Instructions 15.0 General Sequencer Instructions are powerful block instructions. They operate on up to 4 words (64 bits) at a time. There are three sequence instructions: Sequencer Output, Sequencer Input and Sequencer Load.
Chapter 15 Sequencer Instructions Sequencer instructions, when enabled, increment to the next step and then the operation is performed. Figure 15.1 Sequencer Table Step 001 002 003 " " " " " " 024 Word 1 00110101 11000101 01110100 00011101 " " " " " " " 00010101 10100000 Word 2 00011101 11001010 00010111 00110011 " " " " " " " 10100010 10101000 Word 3 10111011 11001011 " " " " " " " " 01010000 01011111 Word 4 01011101 01011111 01010101 01010101 " " " " " " " 10111100 00110011 Figure 15.
Chapter 15 Sequencer Instructions 15.1 Sequencer Output Instruction The Sequencer Output instruction functions in a manner analogous to a mechanical drum sequencer. 15.1.1 Sequencer Output Analogy Consider a music box mechanism containing a cylinder with rows of pegs. As the cylinder turns, the pegs produce tones (output) as they strike the spring resonators. In this analogy, the presence of pegs on the cylinder wall are analogous to 1 in bit locations in the sequencer table.
Chapter 15 Sequencer Instructions Figure 15.3 Sequencer Output Analogy Peg Locations Step 1 2 Drum Cylinder 3 Rotation 4 5 6 Bit Locations Step 1 1 0 1 1 1 1 0 1 1 0 1 1 0 1 0 0 2 Equivalent Sequencer Table 3 4 5 6 15.1.2 Operation of the Sequencer Output Instruction When the rung containing the Sequencer Output instruction goes from false to true, the counter increments to the next step in the sequencer table.
Chapter 15 Sequencer Instructions NOTE: When the rung is false, data is not transferred by the instruction and outputs remain in their last state unless changed by instructions elsewhere in the user program. 15.1.3 Masking Output Data A mask is a means of selectively screening out data. The purpose of the mask in the Sequencer Output instruction is to allow unused bits of output words specified in the instruction to be used for other purposes.
Chapter 15 Sequencer Instructions Figure 15.4 Masking Transferred Data 15.1.4 Instruction Overview 15.1.
Chapter 15 Sequencer Instructions Figure 15.5 SEQUENCER OUTPUT Format SEQUENCER OUTPUT COUNTER ADDR: CURRENT STEP: SEQ LENGTH: WORDS PER STEP: FILE: 110MASK: 010OUTPUT WORDS 1: 010 2: 3: XXX 4: 030 000 001 1 110 010 030 (EN) 17 030 (DN) 15 XXX XXX Numbers shown are default values. Bold numbers must be replaced by user entered values. The number of default address digits initially displayed (3 or 4) will depend on the size of the data table.
Chapter 15 Sequencer Instructions Figure 15.6 SEQUENCER OUTPUT Example Rung 114 | | 14 SEQUENCER OUTPUT COUNTER ADDR: CURRENT STEP: SEQ LENGTH: WORDS PER STEP: FILE: 600MASK: 211OUTPUT WORDS 1: 011 2: 3: 4: 054 007 009 2 621 212 054 (EN) 17 054 (DN) 15 013 When switch 114/14 closes, the Sequencer Output instruction increments to step 008 and controls the 32 outputs corresponding to the specified output words (less those output that are masked).
Chapter 15 Sequencer Instructions the data monitor display of a sequencer instruction and a file instruction should be noted. The Sequencer Output instruction will be used as an example. Each column in the sequencer table represents the data for each output word. This data controls the outputs of the corresponding output word at each step in the sequencer operation. The status of the outputs can be observed in the output address data displayed in the header.
Chapter 15 Sequencer Instructions 15.2 Sequencer Input Instruction The Sequencer Input instruction is a rung-conditioning instruction. It compares machine input and other input data with data stored in the data table for equality. It can be used alone or in a series and/or parallel combination with other rung-condition instructions to determine the status of an output. 15.2.
Chapter 15 Sequencer Instructions 15.2.4 Programming the Sequencer Input Instruction WARNING: The counter address for the Sequencer Input instruction should be reserved for the instruction and the instruction(s) which manipulate the accumulated value. Do not inadvertently manipulate the preset or the accumulated values. Inadvertent changes to these values could result in unpredictable of hazardous machine operation or a run-time error. Damage to equipment and/or personal injury could result.
Chapter 15 Sequencer Instructions An example rung containing the Sequence Input instruction is shown in Figure 15.10. The following parameters have been entered into the instruction: Counter Address – 0055 Current Step – 006 Sequencer Length – 014 Words per Step – 4 File – 0430-0445 Mask – 0214-0217 Input Words – 0110, 0112, 0114, 0115 Figure 15.
Chapter 15 Sequencer Instructions 15.3 Sequencer Load Instruction The Sequencer Load instruction is an output instruction. It is used to load data into table locations such as files or sequencer tables. 15.3.1 Operation of the Sequencer Load Instruction The Sequencer Load instruction receives data from up to 4 independent data table word address(es) specified in the instruction. The load word address(es) can represent input, output and/or storage words. The load word addresses need not be consecutive.
Chapter 15 Sequencer Instructions 15.3.2 Instruction Overview 15.3.3 Programming the Sequencer Load Instruction Output Instruction Key sequence [SEQ] 2 Order of operation is increment then load Counter is indexed by the instruction Instruction does not utilize a mask Requires 4–7 words of user program depending on the number of load words used. WARNING: The counter address for the Sequencer Load instruction should be reserved for that instruction.
Chapter 15 Sequencer Instructions Figure 15.11 SEQUENCER LOAD Format SEQUENCER LOAD COUNTER ADDR: CURRENT STEP: SEQ LENGTH: WORDS PER STEP: FILE: 110INPUT WORDS 1: 010 3: XXX 2: 4: 030 000 001 1 110 030 (EN) 17 030 (DN) 15 XXX XXX Numbers shown are default values. Bold numbers must be replaced by user entered values. The number of default address digits initially displayed 3, 4, or 5 will depend on the size of the data table.
Chapter 15 Sequencer Instructions Figure 15.
Chapter 16 File Logic Instructions 16.0 General This section assumes the reader has Chapter 12, Data Transfer File Instructions, and is familiar with the concepts and terms introduced in that section. 16.
Chapter 16 File Logic Instructions 16.1.1 File to File AND This output instruction operates on the contents of two data files A and B and places the result of the operation AND in a third File R. The logic operation AND compares each bit in File A to the corresponding bit in File B. If the compared bits are both 1, a 1 is stored in the corresponding bit location in File R. If the bits are other than both 1, a 0 is stored in the corresponding bit in File R (Table 16.A). Table 16.
Chapter 16 File Logic Instructions Figure 16.2 FILE TO FILE AND Format FILE TO FILE AND COUNTER ADDR: POSITION: FILE LENGTH: FILE A: 110FILE B: 110FILE R: 110RATE PER SCAN: 030 001 001 110 110 110 001 030 (EN) 17 030 (DN) 15 Numbers shown are default values. Bold numbers must be replaced by user entered values. The number of default address digits initially displayed 3, 4, or 5 will depend on the size of the data table. Initially displayed default values are governed by the I/O rack configuration.
Chapter 16 File Logic Instructions Figure 16.3 FILE TO FILE AND Example Rung FILE TO FILE AND COUNTER ADDR: POSITION: FILE LENGTH: FILE A: 410FILE B: 574FILE R: 610RATE PER SCAN: 16.1.2 File to File OR 050 001 006 415 601 615 006 050 (EN) 17 050 (DN) 15 This output instruction operates on the contents of data Files A and B and places the result of the operation OR in File R (Figure 16.1). The logic operation OR compares each bit in File A to the corresponding bit in File B.
Chapter 16 File Logic Instructions Programming of File to File OR Instruction WARNING: The counter address for the File-to-File OR instruction should be reserved for that instruction. Do not manipulate the counter accumulated or preset values. Inadvertent changes to these values could result in unpredictable or hazardous machine operation or run-time error. Damage to equipment and/or personal injury could result. To program a File-to-File OR instruction, press keys [FILE] 16.
Chapter 16 File Logic Instructions Instruction Overview: Output instruction Key Sequence [FILE] 18 Requires six words of user program Can operate in incremental, distributed complete or complete mode Counter is internally indexed by the instruction Programming File to File XOR Instruction WARNING: The counter address for the File-to-File XOR instruction should be reserved for that instruction. Do not manipulate the counter accumulated or preset values.
Chapter 16 File Logic Instructions Programming File Complement Instruction WARNING: The counter address for the File-to-File Complement instruction should be reserved for that instruction. Do not manipulate the counter accumulated or preset values. Inadvertent changes to these values could in unpredictable or hazardous machine operation or a run-time error. Damage to equipment and/or personal injury could result. To program a File Complement instruction, press [FILE] 13.
Chapter 16 File Logic Instructions Figure 16.5 shows the format of Figure 16.4 after values for the following condition have been entered: COUNTER ADDR – word 050 POSITION – 003 FILE LENGTH – 006 FILE A – 474-501 FILE R – 410-415 RATE PER SCAN – 006. This is the complete mode. The procedure using the data monitor mode for data entry and/or monitor is presented in Chapter 12. Figure 16.
Chapter 16 File Logic Instructions Figure 16.6 WORD TO FILE LOGIC Operations Operation AND, OR, XOR Data Table Word 3 Position 6 File Length File B File R 1 1 2 2 3 3 4 4 5 5 6 6 In this diagram, a logic operation is being performed on the word and step three of File B and the result stored in step three of File R. 16.2.1 Word to File AND This instruction performs an AND operation on the contents of a specified word in the data table and a word from File B.
Chapter 16 File Logic Instructions Counter is not modified by instruction. Needs to be externally indexed by user program. Programming Word to File AND Instruction WARNING: The counter address for the Word-to-File AND instruction should be reserved for the instruction and the instruction(s) which manipulate the accumulated value. Do not inadvertently manipulate the preset or the accumulated values.
Chapter 16 File Logic Instructions Figure 16.8 shows the format of Figure 16.
Chapter 16 File Logic Instructions Table 16.E Truth Table for Logical WORD TO FILE OR Corresponding Bit In Bit In Word File B File R 1 1 0 0 1 0 1 0 1 1 1 0 Instruction Overview: Key sequence: [FILE] 17 Output instructions Requires 5 words of user program Counter is not modified by instruction. Needs to be externally indexed by user program.
Chapter 16 File Logic Instructions (Figure 16.6). If the bits are both 1 or 0, a 0 is stored in the corresponding bit of File R. For other conditions, a 1 is stored in File R (Table 16.F). Table 16.F Truth Table for Logical WORD TO FILE XOR Corresponding Bit In Bit In Word File B File R 1 1 0 0 1 0 1 0 0 1 1 0 Instruction Overview: Key sequence: [FILE] 19 Output instruction Requires 5 words of user program Counter is not modified by instruction. Needs to be externally indexed by user program.
Chapter 17 File Search and File Diagnostic Instructions 17.0 General The File Search instruction locates all words in a file whose data is identical to a specific input word’s data. The File Diagnostic instruction can be used to locate discrepancies between actual and desired states of I/O’s by searching for 1 in the result file of an XOR operation (Section 16.1.3).
Chapter 17 File Search and File Diagnostic Instructions The process continues until the end of the file is reached (position = file length), at which time the done bit is set. The next false-true transition starts the search again at the beginning of the file. If the last word of the file contains a match, the position will equal file length, but the done bit will not be set. On the next false-true transition, the counter will reset to 000 and the done bit is set.
Chapter 17 File Search and File Diagnostic Instructions Figure 17.2 FILE SEARCH Format FILE SEARCH COUNTER ADDR: POSITION: FILE LENGTH: WORD ADDR: FILE: 110- 030 000 001 011 110 030 (EN) 17 030 (DN) 15 Numbers shown are default values. Bold numbers must be replaced by user entered values. The number of default address digits initially displayed 3, 4, or 5 will depend on the size of the data table. Initially displayed default values are governed by the I/O rack configuration.
Chapter 17 File Search and File Diagnostic Instructions Figure 17.3 FILE SEARCH Example Rung FILE SEARCH COUNTER ADDR: POSITION: FILE LENGTH: WORD ADDR: FILE: 400- 17.2 File Diagnostics 200 003 064 141 477 200 (EN) 17 200 (DN) 15 The File Diagnostic instruction can be used for programmed machine diagnostic error detection in conjunction with File-to-File XOR or Word-to-File XOR instructions. First, an XOR operation is performed (Figure 17.
Chapter 17 File Search and File Diagnostic Instructions Figure 17.4 FILE DIAGNOSTIC (A.) XOR Instruction Set Up File A File B 012 File R 310 320 Result Stored in File R XOR 017 315 325 Desired I/O States Actual I/O States (B.) A 1 in File R indicates an error in machine operation. Error File Format 17 14 13 10 07 04 03 0 0 0 1 2 1 00 1 500 0 501 4 502 Word 500 stores error number in 4 digit BCD. Word 501 stores input /output (I/O) in bits 00 03.
Chapter 17 File Search and File Diagnostic Instructions Programming File Diagnostic Instruction WARNING: The counter address specified for the File Diagnostic instruction should be reserved for that instruction. Do not manipulate the counter preset or accumulated values. Inadvertent change to these values could result in hazardous or unpredictable machine operation or a run-time error. Damage to equipment and/or personal injury could result. To program a File Diagnostic instruction, press [FILE] 20.
Chapter 17 File Search and File Diagnostic Instructions COUNTER ADDR – 200 FILE LENGTH – 006 FILE – First word is 320, last word is 325 BASE – First word is 012, last word is 017 ERROR – Error number and location will be stored in words 500 to 502 inclusive The procedure for using the data monitor for data entry or monitor is presented in Chapter 12. Figure 17.
Chapter 18 Troubleshooting Aids 18.0 General The following troubleshooting aids are useful during starting-up and when troubleshooting a system: Bit manipulation and monitor functions Force on and force off functions Forced addressed display Temporary end instruction ERR message display The troubleshooting aids are summarized in Table 18.A. Table 18.
Chapter 18 Troubleshooting Aids Function Mode Key Sequence Description Removing a FORCE OFF Test or Run/Program [FORCE OFF] [REMOVE] Position the cursor on the Image Table bit or bit instruction whose force OFF is to be removed and press the key sequence. Removing all FORCE OFF Test or Run/Program [FORCE OFF] [CLEAR MEMORY] Position the cursor anywhere in program and press key sequence.
Chapter 18 Troubleshooting Aids 18.1.2 Bit Monitor Bit monitor can function when the processor is in any mode. By pressing the key sequence [SEARCH] 53 [Key Sequence of Word Address], the status of all 16 bits of the desired word will be displayed. While the cursor is in the word address field, the [1] and [0] keys can be used to change address digits. The status of the 16 bits in the next highest or next lowest word address also can be displayed by pressing the [↑] or [↓] keys, respectively.
Chapter 18 Troubleshooting Aids All force on or all force off functions can be removed at once in ladder diagram display by breaking communications between the T3 industrial terminal and the processor or by pressing either of the following sequences: [FORCE ON] [CLEAR MEMORY] [FORCE OFF] [CLEAR MEMORY] The on or off status of a forced bit will appear beneath the bit instruction in the rung.
Chapter 18 Troubleshooting Aids 18.4 Temporary End Instruction The Temporary End instruction can be used to test or debug a program up to the point where it is inserted. It acts as a program boundary because instructions below it in user program are not scanned or operated upon. Instead, the processor immediately scans the I/O image table followed by user program from the first instruction to the Temporary End instruction.
Chapter 18 Troubleshooting Aids Section 1.2.3, Industrial Terminal Compatibility.) Those ERR messages do not contain the 4-digit hex value and do not cause a processor fault. If an illegal OP code should occur, the rung containing it can be compared with the equivalent rung in a hard copy printout of the program. A decision must be made either to replace the error with its correct instruction (see Section 4.4.4, Changing an Instruction) or to remove it.
Chapter 19 Special Programming Techniques 19.0 General There are several programming techniques that offer versatile control of the process of machine operation. They include: One-Shot 19.1 One Shot The one-shot programming technique uses a scan counter to set a bit on for one scan only. There are two types of one-shots that can be programmed. Leading Edge Trailing Edge 19.1.
Chapter 19 Special Programming Techniques When bit 112/04 makes a false-true transition, the scan counter begins to increment once each scan. When the accumulated value of the scan counter is equal to 001, bit 203/00 (the one-shot bit) will be on. The next scan, if bit 112/04 is off, the scan counter will be reset to 000. If 112/04 is on, the scan counter will increment to 002. In either case, bit 203/00 will be off and remain off until 112/04 makes another false-true transition. 19.1.
Appendix A Addressing A.0 Appendix Objectives After reading this appendix you should be able to understand: the various addressing modes that you can use with your processor system the system configuration needed for specific addressing modes NOTE: The illustrations show a PLC-2 family processor in the first slot of the 1771 I/O chassis. In a PLC-2/30 system this is replaced with an adapter module. A.
Appendix A Addressing Figure A.1 Hardware/Data Table Addressing Relationships Concept Example Hardware Terminology Hardware Terminology Word Address Input (1) or Output (0) Output: 0 Rack No. (1 7) Rack No.: 1 I/O Group No. (0 7) I/O Group No.: 0 Terminal No. (00 07, 10 17) Terminal No.: 12 Bit Address Word Bit Address Address Data Table Terminology Instruction Address Program Rung Concept XXX | | XX XXX ( ) XX 112 | | 11 010 ( ) 12 Example A.
Appendix A Addressing A.2.1 2 Slot Addressing The processor addresses two I/O module slots as one I/O group. Each physical 2-slot I/O group is represented by a word in the input image table and a word in the output image table. Each input terminal corresponds to a bit in the input image table word and each output terminal corresponds to a bit in the output image table word.
Appendix A Addressing Figure A.2 Illustration of 2 slot Addressing with Two 8 point Input Modules 2 slot I/O Group NOTE: Two 8 point input modules use one full word of the input image table. Input Terminals Input Terminals 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17 Output image table word corresponding to the I/O group. 17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00 unused Input image table word corresponding to the I/O group.
Appendix A Addressing Using 8 Point I/O Modules Figure A.3 Illustration of 2 slot Addressing with 8 point Input and Output Modules I/O Module Group Input Terminals 00 01 02 03 04 05 06 07 Output Terminals 10 11 12 13 14 15 16 17 Output image table word corresponding to the I/O group. 17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00 Used Output bits Unused Output bits Input image table word corresponding to the I/O group.
Appendix A Addressing Using 16 Point I/O Modules High-Density (16-point) I/O modules provide 16 input terminals or 16 output terminals. 16-point I/O modules use a full word in the input or output image table. Two 16-point modules (one input and one output) can be used in a 2-slot I/O group (Figure A.4). Figure A.
Appendix A Addressing that performs the opposite (complementary) function; an input module complements an output module and vice-versa. You can use an 8-point module with 16-point module in a 2-slot group; however, it too must perform the opposite function. In this arrangement, eight bits in the I/O image table are unused. Assigning I/O Rack Numbers When you select 2-slot addressing, each pair of slots (one I/O group) is assigned to the corresponding pair of words in the input and output image tables.
Appendix A Addressing A.2.2 1 Slot Addressing The processor (by way of the adapter) addresses one I/O module slot as one I/O group. Each 1-slot I/O group is represented by a word in the input image table and a word in the output image table. You have 16 input bits and 16 output bits available for each slot. This lets you use any mix of 8 and 16-point I/O modules in the I/O chassis in any order. Thirty-two-point modules must be used in complementary arrangements.
Appendix A Addressing Figure A.6 Illustration of 1 slot Addressing with 16 point I/O Modules 1 slot I/O Group 1 slot I/O Group Input Terminals Output Terminals 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17 Output image table word corresponding to the I/O group. 17 16 15 14 04 03 02 01 00 Input image table word corresponding to the I/O group. 17 16 15 14 04 03 02 01 00 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17 OR Output image table word corresponding to the I/O group.
Appendix A Addressing Figure A.7 Assigning I/O Rack Numbers with 1 slot Addressing Assigned I/O rack number 1 I/O Group No. 01 23 45 Assigned I/O rack number 2 67 01 23 45 67 Í Earlier (Figure A.1), we showed how the 5-digit input or output instruction is associated with a particular I/O module terminal. Now, with two I/O racks you use the instruction address to identify which racks you are communicating with. Figure A.
Appendix A Addressing Figure A.8 Example of 1 slot Addressing I/O Group No. Rack 1 01 23 Rack 2 45 67 01 23 45 67 Í Input Rack I/O Group 1 I/O Group 1 Address 111 Address 121 I/O Group NOTE: When addressing a block transfer module, it must be addressed by the lowest group number that it occupies and at slot 0. For example, a two-slot block transfer module in rack 1, groups 2 and 3 would be addressed (by Rack-Group-Slot) at location 120.
Appendix A Addressing You select 1/2-slot addressing by setting two switches in the I/O chassis backplane switch assembly. See your scanner’s or adapter’s users’ manual for the specific switches and their settings. Figure A.9 illustrates the 1/2-slot addressing concept with a 32-point I/O module. A 32-point I/O module (two 1/2-slot I/O groups) uses two input or two output words of the image table. Module group 0 applies to the upper 16 points; module group 1 applies to the lower 16 points.
Appendix A Addressing Figure A.
Appendix A Addressing Assigning I/O Rack Numbers When you select 1/2-slot addressing, each slot corresponds to two I/O groups. You still assign one rack number to eight groups; however, with 1/2-slot addressing this requires only four slots. Thus, in a single 16 slot chassis, you now can have four I/O racks (Figure A.10). Figure A.10 Assigning I/O rack Numbers with 1/2 slot Addressing Assigned Rack Numbers I/O Group No.
Appendix A Addressing Figure A.11 illustrates addressing 4 modules, each with the same I/O group number, but in four different racks of a single I/O chassis. (This method is explained in Figure A.11.) Figure A.11 Group Address of a Module in Four Different Racks I/O Group No.
Appendix A Addressing 4/5, etc.) or they will not work. (Some two-slot B.T. modules use the lower slave bus on the I/O chassis backplane for intramodule communication.) A.3 System Configurations The PLC-2/30 processor can communicate with the local and remote I/O. Its addressing modes are dependent upon what it is addressing (local or remote I/O) and how it is communicating with its I/O modules.
Appendix A Addressing Table A.A Series B, 1771 Universal I/O Chassis, Addressing Modes vs. I/O Adapters Addressing Mode I/O Adapter Cat. No. I/O Points Per Module 2 slot 1 slot 1/2 slot 1771 AL 8 16 32 A * X X X X X X X 1771 AS 8 16 32 A C X X X X X X X 1771 ASB Series A 8 16 32 A C X A A X A X X 1771 ASB Series B 8 16 32 A C X A A C A A A Legend: A Any mix of modules in the respective points per module category.
Appendix B Number Systems B.0 General There are four numbering systems used with programmable controllers. They are: Decimal Octal Binary Hexadecimal These numbering systems differ by their number sets and place values. B.1 Decimal Numbering System The decimal numbering system uses a number set made up of ten digits: the numbers 0 through 9. All decimal numbers are composed of these digits. The value of a decimal number depends on the digits used and the place value of each digit.
Appendix B Number Systems B.2 Octal Numbering System The octal numbering system is used to address word and bit locations in the data table. Its number set is composed of eight digits: the numbers 0 through 7. Just like all numbering systems, each digit in an otcal number has a certain place value, represented by a power of eight (Figure B.2). The decimal value of an octal number is computed by multiplying each octal digit by its place value and adding these numbers together. Figure B.
Appendix B Number Systems B.3 Binary Numbering System The binary numbering system uses a number set that consists of two digits: the numbers 0 and 1. All information in memory is stored as an arrangement of 1 and 0. Each digit in a binary number has a certain place value expressed as a power of two (Figure B.3). The decimal equivalent of a binary number is computed by multiplying each binary digit by its corresponding place value and adding these numbers together.
Appendix B Number Systems B.3.1 Binary Coded Decimal Binary coded decimal (BCD) uses an arrangement of 12 binary digits to represent a 3-digit decimal number from 000 to 999 (Figure B.4). Each group of 4 binary digits is used to represent a decimal number from 0 to 9. The place values for each group of 4 digits are 20, 21, 22 and 23 (Table B.A). Figure B.
Appendix B Number Systems Table B.A BCD Representation Place Value 23 (8) 22 (4) 21 (2) 20 (1) Decimal Equivalent 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 The decimal equivalent for a group of 4 binary digits is determined by multiplying the binary digit by its corresponding place value and adding these numbers. B.3.
Appendix B Number Systems Table B.B Octal Representation Place Value B.4 Hexadecimal Numbering System 22 (4) 21 (2) 20 (1) Octal Equivalent 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 The hexadecimal numbering system has a number set of 16 digits: the numbers 0-9 and the letters A-F (Table B.C). The letters A-F represent the decimal numbers 10-15 respectively. Table B.
Appendix B Number Systems Figure B.6 Hexadecimal to Decimal Conversion 0 x 163 = 0 1 x 162 = 256 10 x 161 = 160 256 160 7 7 x 160 = 7 42310 0 1 A 7 2 01A716 = 42310 Because each hexadecimal digit represents 4 binary digits, it is easy to convert a hexadecimal number to a binary number. This is done by writing out the 4-bit pattern for each hexadecimal digit (Figure B.7). Figure B.
Appendix C Programming .01 Second Timers C.0 Introduction The bulletin 1772 Mini-PLC-2 Programmable Controller permits you to enter On Delay Timer (TON), Off Delay Timer (TOF), and Retentive Timer (RTO) instructions1 with a 0.01-second time base. These are also referred to as 10-millisecond (10-msec) timers. Timers with a 10-msec time base provide you with greater timing resolution and accuracy than is possible with a 0.1-second time base. Ten-msec timers are used when time delays from 0.02 to 9.
Appendix C Programming .01 Second Timers C.2 Timer Accuracy Given any preset value, a Mini-PLC-2 controller timer is accurate to within one interval of its time base (and this is generally true for any type of timer). Specifically, the timed interval does not exceed the preset interval, but it may be as much as 1 time-base unit shorter than the preset. Let’s illustrate this with the following examples: TON: Time base = 1.0 second; preset value = 100.
Appendix C Programming .01 Second Timers Figure C.1 Timing Diagram Example: [TON], Preset = 003; any time base One unit of time base Internal Clock Pulses 1 Enabled Bit 17 1 Timed Bit 15 1 0 0 0 T=3 2
Appendix C Programming .01 Second Timers C.3 10 Msec Timers - Typical Applications In general, 10-msec timers are used for these functions: monitor events on a high-speed assembly or transfer line, such as that used in canning and bottling machines generate short-duration pulses for accurate positioning control. For example, on a bottling or canning line, photoelectric sensors or electromagnetic proximity switches can be used to detect the movement of bottles/cans.
Appendix C Programming .01 Second Timers Changing the timer presets in this manner also enables you to fine-tune the system without physically adjusting the locations of detection devices. C.4 Hardware/Processor Considerations When considering use of the 10-msec timer, you must consider other timing factors, both within the programmable controller and in the hardware devices. Several examples are: Every input device requires a length of time to change state.
Appendix C Programming .01 Second Timers C.5.1 Scan Time The Mini-PLC-2 Processor performs an I/O scan and then a program scan, in sequence. Scan time is the sum of the times required for both of these scans. (Note that the processor does not scan unused memory, nor does it scan that portion of the memory used to store messages.) During an I/O scan, the processor examines Output Image table bits2 and updates or corrects the ON/OFF signals applied to the output modules.
Appendix C Programming .01 Second Timers The processor can also update a timer only at the instant it is executing that timer instruction. Remember that an integral timing clock (see the preceding section, Timer Accuracy, on the previous page) puts out pulses for the 1.0-, 0.1- and 0.01-second timers. When the 1.0- and 0.1-second timers are used in a program, the timing pulses are always longer than the process or scan time. No special programming is required; these timers will not miss a timing pulse.
Appendix C Programming .01 Second Timers Figure C.2 Typical Timing Diagram for 0.01 Second Timer Start of program scan Scan time = 25 msec (typical) 8 9 msec. Same 0.01 sec. timer rung 8 9 msec. 0.01 sec. timer rung 8 9 msec. Same 0.01 sec. timer rung These multiple entries of the 0.01-second timer rung will help assure that the accuracy of the timer accumulated value is within the accuracy limits discussed above.
Appendix C Programming .01 Second Timers Figure C.3 Typical 0.01 Second Timer Programming 1 Rung No. 21 110 |I| 113 |I| 11005 | | 11006 | | 11014 | | 11300 |/| 030 ( TON ) 0.01 PR 025 AC 000 2 03017 | | 01405 ( ) 3 03015 | | 01410 ( ) 4 03015 | | 11002 | | 01404 ( ) 014 ( IOT ) 35 Legend: 1 Repeat these 5 rungs (typical) 3 or more places in the program. 2 For rung No. 1, when used near the beginning of the program, [ I ] Instructions may be omitted. 3 For rung No.
Appendix C Programming .01 Second Timers Assume the processor is using a 128-word data table and has 1,024 words of memory. If all memory words are used, the program will contain 896 instructions. A program of this size might typically have the following distribution: 546 instructions x 18 µsec = 306 instructions x 28 µsec = 44 instructions x 83 µsec = Total (rounded) 9.8 ms 8.6 ms 3.7 ms 22.0 ms The I/O scan time adds (approx.) The program panel interaction requires about Grand Total 1.0 ms 3.0 ms 26.
Index Numbers 1 slot addressing, A 8 1/2 slot addressing, A 11 10 msec timers programming techniques, C 5 typical applications, C 4 block length, 10 5, 10 17 block transfer, 10 1 basic operation, 10 1 block transfer instructions, 10 4 branch instructions, 4 9 buffering data, 10 12 1771 P2 auxiliary power supply, 2 10 1771 P3, P4, and P5 slot power supplies, 2 11 1771 P7 power supply, 2 11 1771 PSC power supply chassis, 2 11 1777 P2 auxiliary power supply, 2 11 2 slot addressing, A 3 A accessing the da
I–2 Index dependent programming, 7 12 digital cassette recorder, 8 4 displaying and locating errors, 8 6 divide instruction, 6 14 down counter instruction, 5 12 dumping memory content onto data cartridge tape, 8 6 dumping memory content to cassette tape, 8 4 E G get byte - put instruction, 6 8 get byte and limit test instructions, 6 7 get instruction, 6 2 H hardware addressing modes, 2 10 hardware considerations, 2 1 hardware/processor considerations, C 5 hardware/program interface, 3 17 editing, 4 19
Index I–3 ladder diagram logic, 4 2 operating instructions, 4 14 last state switch, 2 6 operation, 10 14 leading edge one shot, 19 1 operation of the sequencer input instruction, 15 10 les and equ instructions, 6 4 loading memory from a data cartridge tape, 8 7 loading memory from cassette tape, 8 4 local system structure, 2 7 local systems, 7 15 local/remote system structure, 2 9 logic instructions, file to file AND, OR, XOR, 5 23 M manually initiated report generation, 9 11 masking input data, 15
I–4 Index shift file down instruction, 13 5 shift file up instruction, 13 3 special techniques, 19 1 timer and counter instructions, 5 14 word to file move instructions, 12 19 put instruction, 6 3 R recursive subroutine (looping) calls, 11 12 relay type instructions, 4 3 4 14 relay type, timer, counter, data manipulations, arithmetic, output override and I/O update, jump, and subroutine instructions, 5 19 remote fault zone programming, 7 9 remote system structure, 2 8 remote systems, 7 15 special progra
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