Programmer (HHP) User guide

Chapter 14
Using High-Speed Counter Instructions
14–8
When a high preset is reached, no counts are lost.
• Hardware and instruction accumulators are reset.
• Instruction high preset is loaded to the hardware high preset.
• If the DN bit is not set, the DN bit is set. The IH bit is also set and the IL,
IV, and IN bits are reset.
• If the DN bit is already set, the OV bit is set. The IV bit is also set and
the IL, IV and IN bits are reset.
• High-speed counter interrupt file (file 4) is executed if the interrupt is
enabled.
The following tables summarize what the input state must be for the
corresponding high-speed counter action to occur:
Up Counter
Input State
High-Sp d
Input Count
(I/O)
Input
Direction (I/1)
Input Reset
(I/2)
Input Hold
(I/3)
HSC Rung
High-Sp
ee
d
Counter Action
Turning
Off-to-On
NA NA NA True Count Up
NA NA NA NA False Hold Count
NA (Not Applicable)
Up Counter with Reset and Hold
Input state
High-Sp d
Input Count
(I/O)
Input
Direction (I/1)
Input Reset
(I/2)
Input Hold
(I/3)
HSC Rung
High-Sp
ee
d
Counter Action
Turning
Off-to-On
NA
Off, On, or
Turning Off
Off True Count Up
NA NA
Off, On, or
Turning Off
On NA Hold Count
NA NA
Off, On, or
Turning Off
NA False Hold Count
Off, On, or
Turning Off
NA
Off, On, or
Turning Off
NA NA Hold Count
NA NA Turning On NA NA Reset to 0
NA (Not Applicable)