User Manual V 1-4.XX User guide

13-4 Understanding the Auto-tuning Procedure
Inverter Dgn1 (parameter 174) is defined as follows:
Bits 14 and 15 are reserved.
Inverter Dgn2 (parameter 175) is defined as follows:
If any hardware fault occurs during the open transistor testing, then
the following occur:
• The hardware fault is saved.
• A phase-to-phase fault is set.
When this bit
is set (1):
Then:
0 A software fault occurred.
1 No motor is connected, or a bus fuse is open.
2 Phase U and W shorted.
3 Phase U and V shorted.
4 Phase V and W shorted.
5 There are shorted modules.
6 A ground fault occurred.
7 A fault occurred before the short module ran.
8 A hardware overvoltage fault occurred.
9 A hardware desat fault occurred.
10 A hardware ground fault occurred.
11 A hardware phase overcurrent fault occurred.
12 There are open power transistor(s).
13 There are current feedback faults.
When this bit
is set (1):
Then:
0 Transistor U upper shorted.
1 Transistor U lower shorted.
2 Transistor V upper shorted.
3 Transistor V lower shorted.
4 Transistor W upper shorted.
5 Transistor W lower shorted.
6 The current feedback phase U offset is too large.
7 The current feedback phase W offset is too large.
8 Transistor U upper open.
9 Transistor U lower open.
10 Transistor V upper open.
11 Transistor V lower open.
12 Transistor W upper open.
13 Transistor W lower open.
14 Current feedback phase U open.
15 Current feedback phase W open.