User's Manual
Table Of Contents
- Table of Contents
- Introduction
- The Hardware
- Installation
- Getting Started
- Inside the Excelsior
- Resizing the Application Window
- Drop-Down Menu Controls
- Tuning the Excelsior
- Receiver Selection
- Mode Selection
- Function Tabs
- Spectrum Scopes
- Recording Functions
- Attenuator
- Preamplifier
- S-meter
- Top Menu Bar
- File
- Options
- Auto-mute RX not in focus
- Enable second RX
- Filter Length
- Front Panel LED
- Display Offset
- Time
- Keyboard Shortcuts
- VSC Set-up
- Audio Buffering
- AMS Capture Range
- Audio Output
- Show Measurements
- Show Data Rates
- Of particular interest to many users will be the CPU load (excessive CPU load may cause sluggish behaviour or freezing of the computer), and Audio latency. Apart from DDC bandwidth, CPU load may be minimized by reducing the Demodulator filter length (...
- Note: When measuring sensitivity using SINAD, it is very important that the Audio Filter is enabled and the cut-off frequencies (and for FM measurements, also the de-emphasis) are set according to the specified test conditions. Proper audio filtering ...
- Show Waterfall Timestamps
- Calibration
- Hand-Off Receiver
- Color scheme
- Restore factory defaults
- Memory
- Scheduler
- Scanner
- Logger
- Plugins
- Power Switch
- Date and Time Display
- Appendix A – SDR and DDC Primer
- Appendix B – Troubleshooting
- Appendix C – USB Interface Diagnostics
- Appendix D – Dealing with Interference
- Appendix E – G39DDCi PCIe Card Connections
- Appendix F – Waterfall Spectrum Palettes
- Appendix G – Recording File Formats
- Appendix H – Compliance Declarations
- Appendix I – Safety Disposal
WiNRADiO G39DDC User’s Guide
112
While this 16 MHz wide band is narrow enough to be digitized by today’s latest
and fast analog-to-digital converters, it is still too wide to be then processed in
real time by most contemporary PCs, and needs to be reduced further. The
most common process for such a reduction is digital down-conversion (DDC)
which typically relies on a special hardware component known as a field
programmable gate array (FPGA).
The process of reducing real time data and thus the usable bandwidth is
known as decimation, and in the Excelsior this first decimation results in a
DDC bandwidth of 4 MHz. There is enough processing power in most modern
computers to allow the user to place two 4 MHz wide windows (independent
receiver channels) anywhere within the 16 MHz IF bandwidth of the Excelsior.
(However, in the USB-based WR-G39DDCe model, the second receiver’s
DDC bandwidth is limited to only 2 MHz due to USB interface data throughput
constraints).
It is interesting (but not recommended to the faint-hearted) to note the
decimation description at
www.wikipedia.org/wiki/Decimation_(Roman_army).
In fact, it is easy to imagine this decimation process to be similar to the mixing
and IF stages of a conventional superheterodyne receiver, with each filtering
stage progressively refining the output of the process.
The Excelsior has two stages of decimation: firstly, from the 16 MHz analog
spectrum to the DDC1 (primary DDC) spectrum, and secondly, from DDC1 to
DDC2 (secondary DDC). The output of the decimation process is sent from the
receiver to the PC, either via the USB (WR-G39DDCe) or the PCI Express
(WR-G39DDCi) interface.
If the USB interface is used, it is important to note that the practical limit of 350
Mbit/s applies to a USB controller that may drive more than one USB port. All
devices connected to it may share the bandwidth and none may achieve the
theoretical 350 Mbit/s.
As the whole DDC spectrum is sent to the PC for processing, it is necessary to
use a ‘modern’ PC, typically with at least a dual core CPU. With slower CPUs,
it may not be possible to achieve the entire potential of the Excelsior, in
particular the ability of processing the entire 4 MHz wide DDC bandwidth.
Once the DDC data is efficiently transferred to the PC, the receiver application
software then continues to processes the data by digital filtering and
demodulation, in two independent receiver channels.