User Manual

User’s Guide OctaMic XTC © RME

27.10 SteadyClock

The SteadyClock technology of the OctaMic XTC guarantees an excellent performance in all

clock modes. Its highly efficient jitter suppression refreshes and cleans up any clock signal, and

provides it as reference clock at the word clock output.

Usually a clock section consists of an analog PLL for external synchronization and several

quartz oscillators for internal synchronisation. SteadyClock requires only one quartz, using a

frequency not equalling digital audio. Latest circuit designs like hi-speed digital synthesizer,

digital PLL, 100 MHz sample rate and analog filtering allow RME to realize a completely newly

developed clock technology, right within the FPGA at lowest costs. The clock's performance

exceeds even professional expectations. Despite its remarkable features, SteadyClock reacts

quite fast compared to other techniques. It locks in fractions of a second to the input signal,

follows even extreme varipitch changes with phase accuracy, and locks directly within a range

of 28 kHz up to 200 kHz.

SteadyClock has originally been de-

veloped to gain a stable and clean clock

from the heavily jittery MADI data

signal. The embedded MADI clock

suffers from about 80 ns jitter, caused

by the time resolution of 125 MHz within

the format. Common jitter values for

other devices are 5 ns, while a very

good clock will have less than 2 ns.

The picture to the right shows the MADI

input signal with 80 ns of jitter (top

graph, yellow). Thanks to SteadyClock

this signal turns into a clock with less

than 2 ns jitter (lower graph, blue).

Using the other input sources of the

OctaMic XTC, word clock, ADAT and

and AES/EBU, you'll most probably

never experience such high jitter

values. But SteadyClock is not only

ready for them, it would handle them

just on the fly.

The screenshot to the right shows an

extremely jittery word clock signal of

about 50 ns jitter (top graph, yellow).

Again SteadyClock provides an extreme

clean-up. The filtered clock shows less

than 2 ns jitter (lower graph, blue).

The cleaned and jitter-freed signal can be used as reference clock for any application, without

any problem. The signal processed by SteadyClock is of course not only used internally, but

also available at the XTC’s word clock output. It is also used to clock the digital outputs MADI,

ADAT and AES/EBU.