Operator`s manual
Table Of Contents
- RS 8000/8600 Getting Started Guide
- Notices
- Table of Contents
- 1 About This Guide
- 2 Introduction
- 3 Hardware Installation
- 3.1 Safety Considerations
- 3.2 Hardware Specifications
- 3.3 Installing the Hardware
- 3.3.1 Verifying Your Shipment
- 3.3.2 Installing the Chassis
- 3.3.3 Installing an AC Power Supply
- 3.3.4 Installing a DC Power Supply
- 3.3.5 Installing the Control Module
- 3.3.6 Installing the Switching Fabric Module (RS8600 only)
- 3.3.7 Installing Line Cards
- 3.3.8 Installing GBIC Modules into Line Cards
- 3.3.9 Installing ATM Physical Media Cards (PHYs)
- 3.3.10 Multi-rate WAN Line Card and WICs
- 3.3.11 SRP Line Cards and Bridge Mate Module
- 3.3.12 Installing SFP Transceivers
- 3.3.13 Attaching the Network Cables to Line Cards
- 4 Initial Configuration
- 4.1 Powering on the RS8000/8600
- 4.2 Starting the Command Line Interface
- 4.3 Configuration Changes and Saving the Configuration File
- 4.4 Setting the Basic System Information
- 4.5 Setting Up Passwords
- 4.6 Setting Up SNMP
- 4.7 Setting the DNS Domain Name and Address
- 4.8 Setting the SYSLOG Parameters
- 4.9 Using Redundant Control Modules
- 5 Managing Software
- Appendix A Troubleshooting
- Appendix B International SaFety Information
- Index
2-48 Riverstone Networks RS 8000/8600 Switch Router Getting Started Guide
Hardware Overview Introduction
The following table maps the pin assignments for Riverstone’s LFH-60 high density connectors for the Quad
Serial – C/CE line cards.
Figure 2-34 shows the pin positions in the LFH-60 high density connector.
Table 2-43 Quad serial cables and connector types
Riverstone Part Number CSU/DSU Connector Type Standard
SYS-SV35-DTE Two (2) V.35 34-pin connectors V.35
SYS-S530-DTE Two (2) DB-25 25-pin connectors EIA-530
SYS-S449-DTE Two (2) DB-37 37-pin connectors RS-449
SYS-SX21-DTE Two (2) DB-15 15-pin connectors X.21
Table 2-44 Pin assignments for quad serial line cards
Pin Signal Pin Signal Pin Signal Pin Signal
1 P1_GND 16 P2_TXC_A 31 P1_GND 46 P2_TXD_A
2 P1_MODE[2] 17 P2_TXC_B 32 P1_MODE[0] 47 P2_TXD_B
3 P1_CTS_B 18 P2_DCD_A 33 P1_DCD_B 48 P2_RTS_A
4 P1_CTS_A 19 P2_DCD_B 34 P1_DCD_A 49 P2_RTS_B
5 P1_RTS_B 20 P2_MODE[1] 35 P0_RXD_B 50 P2_DSR_A
6 P1_RTS_A 21 P2_GND 36 P0_RXD_A 51 P2_DSR_B
7 P1_SCTE_B 22P2_GND 37Reserved 52P2_LL_A
8 P1_SCTE_A 23 P1_TXD_A 38 P2_GND 53 P2_SHIELD
9 P1_GND 24 P1_TXD_B 39 P2_MODE[0] 54 Reserved
10 P2_GND 25 P1_TXC_A 40 P2_CTS_B 55 P1_RXC_A
11 P2_MODE[2] 26 P1_TXC_B 41 P2_CTS_A 56 P1_RXC_B
12 P2_RXD_B 27 P1_DSR_A 42 P2_DTR_B 57 P1_DTR_A
13 P2_RXD_A 28 P1_DSR_B 43 P2_DTR_A 58 P1_DTR_B
14 P2_RXC_B 29 P1_MODE[1] 44 P2_SCTE_B 59 P1_LL_A
15 P2_RXC_A 30 P1_GND 45 P2_SCTE_A 60 P1_SHIELD