User guide

BIOS Setup
BIOS Setup
SDRAM Cycle
Length
This field controls SDRAM CAS latency clock cycles.
Leave on default value.
The choice: 3 (Default), 2
Unbuffered
DRAM Clock
This item allows you selecting DRAM clock to fixed bus
clock.
The choice: HCLK-33M, HCLK+33M, Host CLK
(Default)
Register DRAM
Clock
This item allows you selecting Register DRAM clock to
fixed bus clock.
The choice: 100MHz (Default), 133MHz
Memory Hole
This option specifies the location of an area of memory
that cannot be addressed on the ISA bus.
The choice: Disable (Default), 15 MB-16 MB.
P2C/C2P
Concurrency
Enable the PCI to CPU / CPU to PCI concurrency.
The choice: Enable (Default), Disable.
Fast R-W Turn
Around
Leave on the default for SDRAM compatibility
The choice: Enable (Default), Disable.
System BIOS
Cacheable
When set to Enabled, the contents of the F0000h
system memory segment can be read from or written to
cache memory. The contents of this memory segment
are always copied from the BIOS ROM to system RAM
for faster execution.
The choice: Enable (Default), Disable.
Video RAM
Cacheable
Select Enable allows caching of the video BIOS,
resulting in better system performance. However, if
any program writes to this memory area, a system error
may result.
The choice: Enabled, Disable (Default).
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