Datasheet

RIGOL
6
Vertical
Bandwidth (-3 dB)
(50 Ω)
MSO/DS2302A/2302A-S: DC to 300 MHz
MSO/DS2202A/2202A-S: DC to 200 MHz
MSO/DS2102A/2102A-S: DC to 100 MHz
MSO/DS2072A/2072A-S: DC to 70 MHz
Single Bandwidth
(50 Ω)
MSO/DS2302A/2302A-S: DC to 300 MHz
MSO/DS2202A/2202A-S: DC to 200 MHz
MSO/DS2102A/2102A-S: DC to 100 MHz
MSO/DS2072A/2072A-S: DC to 70 MHz
Vertical Resolution
Analog channel: 8 bit
Digital channel: 1 bit
Vertical Scale
[3]
When the input impedance is 50 Ω: 500 μV/div to 1 V/div
When the input impedance is 1 MΩ: 500 μV/div to 10 V/div
Offset Range
When the input impedance is 50 Ω:
500 μV/div to 50 mV/div: ±2 V
51 mV/div to 200 mV/div: ±10 V
205 mV/div to 1 V/div: ±12 V
When the input impedance is 1 MΩ:
500 μV /div to 50 mV/div: ±2 V
51 mV/div to 200 mV/div: ±10 V
205 mV/div to 2 V/div: ±50 V
2.05 V/div to 10 V/div: ±100 V
Bandwidth Limit
[1]
MSO/DS2302A/2302A-S/2202A/2202A-S: 20 MHz/100 MHz
MSO/DS2102A/2102A-S/2072A/2072A-S: 20 MHz
Low Frequency
Response (AC
Coupling, -3 dB)
≤5 Hz (on BNC)
Calculated Rise Time
[1]
MSO/DS2302A/2302A-S: 1.2 ns
MSO/DS2202A/2202A-S: 1.8 ns
MSO/DS2102A/2102A-S: 3.5 ns
MSO/DS2072A/2072A-S: 5 ns
DC Gain Accuracy
[3]
±2% full scale
DC Offset Accuracy ±0.1 div ± 2 mV ± 1% offset value
Channel to Channel
Isolation
DC to maximum bandwidth: >40 dB
Vertical (Digital Channel)
Threshold 1 group with 8 channels adjustable threshold
Threshold Selection
TTL (1.4 V)
5.0 V CMOS (+2.5 V)
3.3 V CMOS (+1.65 V)
2.5 V CMOS (+1.25 V)
1.8 V CMOS (+0.9 V)
ECL (-1.3 V)
PECL (+3.7 V)
LVDS (+1.2 V)
0 V
User
Threshold Range ±20.0 V, in 10 mV step
Threshold Accuracy ±(100 mV + 3% of threshold setting)
Dynamic Range ±10 V + threshold
Minimum Voltage
Swing
500 mVpp
Input Impedance //101 kΩ
Probe Loading ≈8 pF
Vertical Resolution 1 bit