Specifications

Chapter 2 Command System RIGOL
M300 Programming Guide 2-189
STATus Command Subsystem
 STATus:ALARm:CONDition?
 STATus:ALARm:ENABle
 STATus:ALARm[:EVENt]?
 STATus:OPERation:CONDition?
 STATus:OPERation:ENABle
 STATus:OPERation[:EVENt]?
 STATus:PRESet
 STATus:QUEStionable:CONDition?
 STATus:QUEStionable:ENABle
 STATus:QUEStionable[:EVENt]?
Explanation: The M300 status system is as shown in Figure 1-2.
STATus:ALARm:CONDition?
Syntax
STATus:ALARm:CONDition?
Description
Read and clear the condition register of the Alarm Register set.
Explanation  The condition register is read-only and will not be cleared when you read the register.
 Sending the
*CLS command will clear the alarm queue and the "Queue Not Empty"
bit (bit4) in the condition register.
 The bit definitions of the alarm condition register are as shown in the table below.
Bit
Bit Name
Weight
Definition
0-3
Not Used
1-8
Always be 0.
4
Queue Not Empty
16
The alarm queue is not empty.
5
Not Used
32
Always be 0.
6
Alarm 1
64
Alarm 1 is triggered.
7
Alarm 2
128
Alarm 2 is triggered.
8
Alarm 3
256
Alarm 3 is triggered.
9
Alarm 4
512
Alarm 4 is triggered.
10-11
Not Used
1024-2048
Always be 0.
12
Lower Limit
4096
A lower limit alarm has occurred.
13
Upper Limit
8192
An upper limit alarm has occurred.
14-15
Not Used
16384-32768
Always be 0.
Return
Format
The query returns an integer which corresponds to the binary-weighted sum of all the bits
in the register. For example, if bit 4 (16 in decimal) and bit 12 (4096 in decimal) are
enabled, this command will return 4112 (#b1000000010000).
Example STAT:ALAR:COND?
The query retruns 4112.
Related
commands
STATus Command Subsystem
STATus:ALARm:ENABle
STATus:ALARm[:EVENt]?
SYSTem:ALARm?
*CLS