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ManualsBrandsRigol ManualsComputer equipmentM300 Series
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Chapter 1 Programming Overview RIGOL
M300 Programming Guide 1-9
Read the event register from the relative register group (only the corresponding bits in the event
register of the relative register group are cleared).
The status byte enable register is cleared when:
Send the *SRE
0 command.
The status byte enable register will be cleared when restarting the instrument after sending the
*PSC
1 command to set the instrument to clear all the bits in the enable register at power-on. On
the
contrary, the status byte enable register will not be cleared when restarting the instrument
after sending the
*PSC 0 command to set the instrument to not clear all the bits in the enable
register at power-on.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Alarm Register
Operation Status Register
Standard Event Status Register
Output Buffer
Status Byte Register
TOT Overflow
MEM Overflow
Scanning
Config Change
Instrument Locked
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2
4
8
16
32
64
128
256
512
1024
2048
4096
8192
16384
32768
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2
4
8
16
32
64
128
256
512
1024
2048
4096
8192
16384
32768
1
2
4
8
16
32
64
128
1
2
4
8
16
32
\
128
CR
CR
EVR
EVR
EVR
CR
ENR
ENR
ENR
ENR
Volt Overload
Curr Overload
Res Overload
Temp Overload
STATus:QUEStionable
:
CONDition?
STATus:QUEStionable
[:
EVENt]?
STATus:QUEStionable
:
ENABle <enable value>
STATus:QUEStionable:ENABle?
..
.
Operation Complete
Query Error
Device Error
Execution Error
Command Error
Power On
*ESR?
*
ESE <enable
_val>
*
ESE?
STATus:OPERation:CONDition? STATus:ALARm[:EVENt
]?
STATus:
OPERation:ENABle <enable_value>
STATus:OPERation:
ENABle?
*STB?
*SRE
<enable_val>
*
SRE?
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Questionable Status Register
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2
4
8
16
32
64
128
256
512
1024
2048
4096
8192
16384
32768
CR
EVR ENR
Alarm 1
Alarm 2
STATus:ALARm:CONDition? STATus:ALARm
:EVENt
?
STAT:ALARm:ENABle <enable_val>
STAT:ALARm
:ENABle
?
1
2
.
.
.
99
100
Alarm1
Queue
Alarm 3
Alarm
4
Alarm Overflow
SYSTem
:ALARm?
1
2
20
Error Queue
..
.
Alarm
1
Alarm 2
Alarm 3
Alarm 4
Lower Limit
Upper Limit
Calibrating
Self Test
WFT
USB MSD detected
Global Error
Busy
Mem Threshold
Settings Changed
1
2
.
.
.
99
100
Alarm2 Queue
1
2
.
.
.
99
100
Alarm3 Queue
1
2
.
.
.
99
100
Alarm
4
Queue
Figure 1-2 M300 Status System Structure Diagram