Specifications

RIGOL Chapter 1 Programming Overview
1-8 M300 Programming Guide
SCPI Status System
This chapter introduces the SCPI status system of M300.
M300 status system is shown in Figure 1-2. The five register groups are used to record a variety of
conditions and status of the instrument. Each register group contains multiple underlying registers
(condition register, event register and enable register).
 Condition register
The condition register monitors the instrument status continuously and the status of each bit is
updated in real time. The condition register is read-only and the bits will not be cleared when you read
the register. It returns a decimal value corresponding to the sum of the binary weights of all the bits in
the register when you query the condition register.
 Event register
The event register latches the various events from the condition register. If the bit corresponding to an
event is set to 1, the subsequent events will be ignored. The event register is read-only. Once a bit is
set to 1, it remains set until cleared by a query command (such as
*ESR?) or the *CLS command. It
returns a decimal value corresponding to the sum of the binary weights of all the bits in the register
when you query the event register.
 Enable register
The enable register defines whether to report the event in the event register to the status byte register
group or not. The enable register could be read and written. You can use the
STATus:PRESet command
to clear all the bits in the enable register and use the *PSC
1 command to configure the instrument to
clear all the bits in the enable register at power-on. To enable the bits in the enable register, write a
decimal value corresponding to the sum of the binary weights of all the bits in the enable register.
 The Status Byte Register
The status byte register group reports the events from other register groups. For example, the system
error is reported to bit2 (Error generate). Clearing the event register of the relative register group will
clear the corresponding bits in the condition register of the status byte register group. For example,
clearing the error queue will clear bit2 (Error generate) in the condition register of the status byte
register group. The bit definitions of the status byte register are as follws.
Bit
Weight
Name
Explanation
7
128
Operation
Status Summary
One or more bits are set in the operation status register
(the bits must be enabled, refer to the
STATus:OPERation:ENABle command).
6
64
Master
Summary
One or more bits are set in the status byte register.
5
32
Standard Event
Status Summary
One or more bits are set in the standard event status
register (the bits must be enabled, refer to the *ESE
command).
4
16
Message
Available
Data is available in the output buffer.
3
8
Questionable
Status Summary
One or more bits are set in the questionable status register
(the bits must be enabled, refer to the
STATus:QUEStionable:ENABle command).
2
4
Error Queue
One or more errors have been stored in the Error Queue.
1
2
Alarm Summary
One or more bits are enabled in the alarm register (the bits
must be enabled, refer to the STATus:ALARm:ENABle
command).
0
Not Used
Not Used
Always be 0.
The status byte condition register is cleared when:
 Send the
*CLS command.