Instructions

RIGOL Chapter 2 Command System
2-24 DG2000 Programming Guide
Remarks
 "operation complete" refers to that all the previous commands that have been sent, including the *OPC
command, are executed completely.
 You can also use the *OPC (operation complete) or *OPC? (operation complete query) command to set
the system to output a signal when finishing the sweep or burst. The *OPC command sets the OPC
(operation complete) bit in the standard event register to 1 after all the previous commands that have
been sent are executed. When the bus is used to trigger the sweep or burst, the system can execute
other commands before this bit is set to 1. The *OPC? command returns 1 to the output buffer after all
the previous commands that have been sent are executed and the system cannot execute any other
command before completing executing this command.
 Sending the *OPC? command (query command) and reading the result can ensure synchronization.
 When setting the instrument by programming (by executing command strings), taking the *OPC
command as the last command of the command queue can determine when the command queue is
completed (the OPC (operation complete) bit in the standard event register is set to 1 after the
command queue is completed).
Return Format
The query returns 1 or 0.
Example
*OPC /*Configures the instrument to set the OPC (operation complete) bit in the standard
event register to 1 after all the previous commands that have been sent are
executed.*/
*OPC? /*Queries whether all the previous commands that have been sent are executed. If
yes, the query returns 1 to the output buffer.*/
*PSC
Syntax
*PSC {0|1}
*PSC?
Description
Enables or disables clearing of the status byte enable register and standard event enable register at
power-on.
Queries whether to clear the status byte enable register and standard event enable register at power-on.
Parameter
Name
Type
Range
Default
{0|1}
Discrete
0|1
1
Remarks
 The *PSC 1 command means clearing the status byte enable register and standard event enable
register at power-on. The *PSC 0 command means the status byte enable register and standard event
enable register will not be affected at power-on.
 You can also send the *SRE
0 and *ESE 0 commands to clear the status byte enable register and
standard event enable register respectively.
Return Format
The query returns 0 or 1.
Example
*PSC 1 /*Enables clearing of the status byte enable register and standard event enable register at
power-on.*/
*PSC? /*Queries whether to enable or disable the clearing of the affected registers at power-on. The
query returns 1.*/