Data Sheet

Richlink Technology Corp.
11
RL62M01A BLE Module Datasheet
Copyright © 2020 Richlink Technology Corp. All rights reserved.
Boot up by HW_RST_N pin, power on timing is shown in below figure.
VBAT, VDDIO
HW_RST_N
VDDCORE
40MHz XTAL
T
VBAT_RISE
< 540us @VBAT=1.8V
T
VBAT_RISE
< 1ms @VBAT=3.3V
T
RST
> 200s
T
POR2VDDCORE
> 7msec
(typical: 18msec)
T
POR2VXTAL
> 12msec
(typical: 32msec)
⚫ UART Characteristics
RTS_OUT
UART_RX_IN
End of STOP BIT
T
D_RTS
UART_TX_OUT
CTS_IN
T
D_CTS
T
SET_CTS
End of STOP BIT
Parameter
Description
Note
Min.
Typ.
Max.
Unit
T
D_RTS
Timing between UART_RX_IN stop bit and
RTS rising edge when RX FIFO is full
0.5
ns
T
D_CTS
Timing between CTS falling edge and
UART_TX_OUT first bit
25
ns
T
SET_CTS
Timing between CTS rising edge and
UART_TX_OUT stop bit
75
ns