Operating instructions

5 Circuit Description

The following descriptions should be read as an aid to understanding the block and

schematic diagrams given in the appendix of this manual.

There are 9 sheets in the schematic in all.

5.1 T50 Master Schematic (Sheet 1)

Sheet 1, referred to as the “T50 Master Schematic”, is a top level sheet, showing five

circuit blocks, and their interconnection with each other, as well as the interconnection

with all connectors and external switches.

JP12 is the connector, on the printed circuit board, for the microphone input.

P3 represents the rear female DB25 connector.

J1 is the nominal 1W RF output (BNC) connector, which is used to connect to the

External Power Amplifier.

J4 is an optional BNC connector for an external reference clock. If an external

reference clock, with power level from +5 to +26dBm is attached here, the firmware

will automatically track the channel VCO to the reference.

Note that the external reference frequency is limited to:

500kHz, or any multiple

any multiple of 128KHz greater than or equal to 512kHz

any multiple of 160KHz greater than or equal to 480kHz

and cannot be greater than 10MHz in Rev 4 or older versions. In Rev 5, the external

frequency can be as high as 20MHz.

P1 is the front panel DB9 RS-232 connector for attachment to a terminal, a terminal

emulator, or to an IBM PC running the WinTekHelp software.

JP2 is for the attachment of an LCD display module. This has been included for later

development. This connector, is not normally fitted

JP3, and JP4 are specialised connectors for test and factory configuration use only.

RV100 represents the front panel LINE potentiometer.

SW1 represents the PTT test pin.

D102, D103, and D104 represent the three front panel LEDs.

5.2 Microprocessor (Sheet 2)

Sheet 2 describes the basic microprocessor circuitry.

The core CPU is the Motorola XC68HC12A0. It is

configured in

8 bit data width

mode.

The CPU is clocked by a 14.7456MHz crystal oscillator circuit (top left) comprising the

JFET Q202, and two switching transistors Q203 and Q204.

The CPU contains an 8 channel A/D converter whose inputs are identified as AN0,

AN1, …, AN7.

AN7 and AN6 are used as LOCK detect inputs from the two Phase Locked Loop (PLL)

circuits (see 5.6)

AN5 is used to sense whether or not the dc supply is within spec or not.