Operating instructions

18
The VCO frequencies are controlled by the bias applied to D701 and D704 respectively,
which is set by signals MOD_PLL_IN and CHAN_PLL_IN. These signals are the
phase detector outputs from the Modulation PLL and the Channel VCO respectively
(see Sheet 6).
Diodes D700 and D703 are used to provide some AGC for the JFETs. These Schottky
diodes will increase the –
ve bias on the gate of the JFETs (thereby decreasing the drain
current) if the oscillation level should increase, and similarly the gate bias will reduce if
the –
ve peaks of the oscillation should reduce.
The Modulation bias is also adjusted by the modulation input (MOD_IN). This signal is
amplified by a VCA.
The BALANCE DAC output is converted to a current by U707
and Q700, and that then is used to set the gain of the VCA. The output of the VCA is
then attenuated by R725/R729, and this bias is then applied to varactor D701. Note that
the modulation bias is in anti-phase to the PLL bias.
Each VCO has its own gyrator feed circuit (Q707 and Q702). This is done to remove
any possible noise on the voltage rails from modulating either VCO.
The drain current of each VCO can be switched off or on by MOSFETs Q701 and
Q703. Q701 is switched on when MOD_VCO_EN is high. MOD_VCO_EN is the user
programmable digital output from DAC U601 (see Sheet 6). Q703 is switched on when
the CPU output CHAN_VCO_EN (see Sheet 2) is high.
The output of each VCO is “sniffed”, by a high impedance attenuator. In the
modulation VCO, R737 in series with the 50 ohm input impedance of U702 forms this
attenuator. In the Channel VCO, R745, R736, and the input impedance of U706 form
one such attenuator, and R741 in series with the input impedance of U703 forms the
other. Note that there is a low pass filter in the front of U702, and U706 to reduce the
level of spurious signals generated by
intermod in these two amplifiers,
U702 amplifies the modulation VCO signal, which is then amplified again by U701,
then filtered to reduce harmonics, before arriving at the LO input of MX700 at a level of
around +5 - +7dBm. The output of U702 also has a low pass filter to reduce the level of
harmonics arriving at the mixer.
The output of the MOD VCO is also attenuated by R733, and then re-amplified before
becoming MOD_VCO_OUT. MOD_VCO_OUT is then passed to the Modulation PLL
(U602, see Sheet 6).
U705’s primary role is to ensure that noise that becomes coupled by the PLL chip, back
onto its VCO input, does not couple back into the path to the mixer. If this isn’t done,
then the mixer’s LO input contains many harmonics of the reference oscillator.
U703 performs both an amplification role, and an isolation role similar to U703’s. Its
output (CHAN_VCO__OUT) is fed back to the Channel PLL (U604, see Sheet 6).
The output of U706 is attenuated by the network R714, R742, and R724, and it is
filtered to reduce harmonics as much as possible. This filtered VCO output is then
brought to the RF pin of the mixer at a level of about –19dBm.
The output of the mixer is then run through a low pass filter to remove frequencies other
than (Fmod - Fvco). U700 then amplifies this signal to a level of about –6 to –8dBm.
The external output signal of T/R_RELAY, which is asserted low whenever the exciter
is keyed up, is used to switch MOSFET Q706 off. When Q706 is off, amplifier U700 is
enabled. When T/R_RELAY is high, then U700 is deprived of bias current and
VCO_OUT is then completely disabled.