Operating instructions

The digital POT performs two functions. It is used to help set the maximum CTCSS

tone deviation. It does this in conjunction with U500, as it is also possible for the

CTCSS tones that are launched by U500 to be adjusted using software.

The second function of the digital POTs is enabled when U301D is enabled. The level

of attenuation by the digital POT is adjusted as part of the calibration procedure to set

the tone deviation caused when a signal is applied to the tone input.

R526, D502, and D503, form a limiter, that prevents any signal arriving from the TONE

pair from ever exceeding 3kHz deviation.

5.6 Frequency Synthesiser (Sheet 6)

This circuit also includes Sheet 7 as a block diagram. Sheet 7 contains the schematic

for the two Voltage Controlled Oscillators.

There are two complete Phase Locked Loops. One is called the Modulation PLL, and

the other is referred to as the Channel PLL.

The Modulation PLL does change frequencies slightly, but by less than +/- 240kHz.

The Channel PLL is the principal PLL that changes frequencies when the exciter

changes frequency.

As its name suggests, modulation is performed on the Modulation PLL.

The modulation is a conventional 2 point FM modulation. Modulation by signals,

whose frequency components are well below the PLL loop frequency, is effected by

modulating the reference oscillator of the Modulation PLL.

Frequencies well above the

PLL loop frequency are effected by modulating the Modulation VCO directly, and

frequencies in the cross-over region are a combination of the two.

The heart of this schematic are the two PLL chips U602, and U604.

Each is, in fact, a dual PLL chip, but only one PLL, in each, is used. All that is used of

the second PLL chip is its dividers. The outputs of these dividers can be switched to the

FoLD output pin, which is then converted to a square wave by a further division of 2 by

U606A and U606B.

By using the second

PLL’s dividers it is possible to divide the reference oscillator, and

the VCO output down to frequencies that can be handled by the Timer inputs of the

CPU, without causing excessive interrupt load to the CPU.

5.6.1 The Modulation PLL

U602 and the Modulation VCO (see Sheet 7) form the modulation PLL. U602 acts as

its own crystal oscillator for its reference oscillator. X600 is a 5ppm, 12MHz, crystal.

Its resonant point is adjusted by the bias applied to varactor D600.

The bias applied to varactor D600 is a combination of the potentials at two DAC

outputs (MOD_ADJ and MOD_ADJ_FINE), plus the modulating signal arriving at

MOD_IN (which is the same signal as MOD_OUT in Sheet 3).

The summing of these three voltages is performed by U607.

The Phase detector output of the PLL chip is then passed through the loop filter network

defined by C612, R618, C625, R617, C613, and C718 (see Sheet 7). L713 is used to

filter out any residual noise (outside of the audio bandwidth), including the phase

detector frequency, and/or any switch-mode noise from the dc voltage rails.

The loop filter signal is then fed as a control voltage to the Modulation VCO

(MOD_PLL_IN).