Operating instructions

CH_EN is a serial bus select. It is brought out to the rear panel and is used to interface

to the channel encoder on the rear daughter-board. (See 5.1)

Any GPS pulses are isolated from the on-board electronics by the opto-isolator U212.

The output of that opto-isolator is then connected to the GPS timer input of the CPU.

This has been included for future use to be able to auto-adjust the reference oscillator

frequencies to low, or high frequency clock pulses from an external clock reference of a

GPS receiver.

TERM_EN2 and TERM_EN1 are used to enable (when low) 600 ohm termination of

Line2, and Line1 respectively. (See 5.3)

The Fo outputs from the Modulation PLL and the Channel PLL are divided by two, and

these are called FO_MOD_2 and FO_CHAN_2 respectively. They should be 200Hz

square waves, except for brief periods when frequencies are being changed. (See 5.6)

ECLK is a pin that at start-up only, should have the CPU system clock of 7.3728MHz

on it.

TX_LED, ALARM_LED, are CPU outputs that drive (when low) the TX LED, and the

ALARM LED on.

T/R_RELAY_H, when high, drives the T/R RELAY output low, and also enables the

RF power amplifier. The T/R RELAY output can activate at least one conventional

12V relay. (See 5.1)

SCLK, and MOSI are used as the core of a serial bus. SCLK is a clock pin, and MOSI

is a bi-directional data pin.

PA_CS is a serial select pin. It is passed, via the rear DB25 connector to the External

Power Amplifier (PA). (See 5.1)

DBGTX_TTL, DBGRX_TTL are RS232 transmit and receive (TTL) data pins which

are connected to the debug port after conversion to/from RS232 compatible voltage

levels by U202 and U201.

TXD_TTL, RXD_TTL, RTS_TTL, CTS_TTL, DTR_TTL, DSR_TTL, are RS232 data

pins which are connected to the main front panel serial port after conversion to/from

RS232 compatible voltage levels by U202 and U201.

PTT_uPHONE is a CPU input and it reflects the state of the PTT pin on the microphone

handset.

TONE_INT is a CPU input that comes from the FX805 (U500). This pin is used to

indicate when a Tone has been decoded, or there is some other need to service the

FX805. As yet, this pin is not used in the T50. (See 5.5)

LOOP_DET is a CPU pin that is asserted low if there is dc loop current detected

through the centre tap input of Line2. (See 5.3)

FILTER_OFF is a CPU output that is used to by-pass, when low, the low pass filter in

the Tone Input Circuitry. (See 5.5)

PTT-in is an input from the rear DB25 connector that causes the INT pin of the CPU to

be asserted (low) when 1mA of current is drawn via that pin. If PTT-in is pulled to

ground, through a resistance of at most 3.9kohms, it will cause INT to be asserted. If it

is pulled low via a 2K2 resistor, and as many as three diodes in series, it will still cause

the INT pin to be asserted. This latter example shows that quite complex diode logic

can be used on this pin.

BKGD is a bi-directional I/O pin used to communicate with the core of the CPU. It is

connected to the debug port and is utilised by specialised hardware to control the CPU

externally, even without any firmware being present in the Flash.