Operating instructions

RF Technology R50 Page 7
program channel information. See the
WinTekHelp
users manual for further
information.
5 Circuit Description
The following descriptions should be read as an aid to understanding the block and
schematic diagrams given in the appendix of this manual.
There are 7 sheets in the schematic in all.
5.1 R50 Master Schematic (Sheet 1)
Sheet 1, referred to as the "R50 Master Schematic", is a top level sheet, showing four
circuit blocks, and their interconnection with each other, as well as the
interconnection with all connectors and external switches.
P1 is the front panel DB9 RS-232 connector for attachment to a terminal, a terminal
emulator, or to an IBM PC running the WinTekHelp software.
P3 represents the rear female DB25 connector.
J1 is the terminal on print circuit board, it is connected to the internal load speaker.
JP2 is for the attachment of
an LCD display module. This has been included for later
development.
JP3 is a specialised connector for test and factory configuration use only.
D102, D103, and D104 represent the three front panel LEDs.
5.2 Microprocessor (Sheet 2)
Sheet 2 describes the basic microprocessor circuitry.
The core CPU is the Motorola XC68HC12A0. It is configured in
8 bit data width
mode.
The CPU is clocked by a 14.7456MHz crystal oscillator circuit (top left) comprising
the JFET Q202, and two switching transistors Q203 and Q204.
The CPU contains an 8 channel A/D converter whose inputs are identified as AN0,
AN1, …, AN7.
AN7 is used as LOCK detect inputs from the Locked Loop (PLL) circuits (see 5.6)
AN6 is used to sense the noise squelch level setting.
AN5 is used to sense whether or not the dc supply is within spec or not.
AN4 is used to sense the audio from the discriminator, so the R50 receiver can be
used as a deviation meter.
AN3 and AN1 are inputs from the PLL circuits that sense the bias voltage on the VCO
control varactor for each VCO.
AN2 is used to sense the carrier squelch level setting.
AN0 is used to sense the RF input signal strength which is detected by the IF chip.
FRDY is an output from the flash. It goes low when the Flash starts to write a byte of
data, or erase a block, or erase the whole chip, and it returns to its default high
state when the action requested has completed.