User's Manual

Eclipse2 Technical Manual V1.5 Page 13 of 16
Header (H4) is used only for emergency system booting purpose, do not assert jumper into this
header.
Clock generator
the 12.8MHz TCXO (X1) output is buffered (by U26) and divided by 4 (U29) to provides PLL
reference frequency for exciter and receiver. The frequency doubler double 12.8MHz frequency to
25.6MHz to provide system clock for digital IF receiver.
Voltage regulators
There are nine voltage sources generated by the voltage regulator
VTX +12.5V DC for TX module
VRX +12.0V DC for RX module
D3V3 +3.3V DC for Processor (Master) board and 3V TTL logic
A3V +3.15V DC for analog 3V rail
+12V +12.0VDC for analog circuits
+5V +5V DC for TCXO and 5V TTL logic
+1V8 +1.8V DC for Flash core supply on the Processor (Master) board
-20V -20.0V DC for TX and RX VCO bias setting
-12V -12.0VDC for analog circuits
The input power supply voltage is 13.8VDC, LDO (U19, U22) provides 12.5V (Imax = 1.5A) and
12V DC (Imax = 800mA) for TX and RX module. Switch mode DC-DC converter (U20) generates
digital 3.3V DC rail (Imax=2A) for the Processor board and Interface board, then regulated to
3.15V analog DC rail by LDO (U21) for 3V analog circuits in the transceiver.
The DC-DC converter (U23) provides –20V negative supply voltage for VCO bias amplifier (U4).
Voltage regulator (U24) generates –12V DC supply analog circuits of the interface board.
RF modules
TX module
The TX module can be divided into the VCO, PLL, PA and the Data storage section.
The Voltage Controlled Oscillator (VCO)
The Voltage Controlled Oscillator uses a junction FET (Q2) which oscillates at the required
transmitter output frequency. Varactor diodes (D2, D9, D10, and D11) are used by the PLL and
bias control circuits to keep the oscillator on the desired frequency. Transistor Q1 is used as an
active filter to reduce the noise on the oscillator supply voltage.
The VCO is keyed ON by the RISC processor through Q3, It is keyed ON when any of the PTT
inputs are active or self-calibrations, but OFF at all other times. The VCO output is amplified by
monolythic amplifier U4 before being fed to the PLL chip (U10).
The Phase Locked Loop (PLL)
The frequency reference for the PLL is from the Interface board via a 20pin connector. A
fractional-N PLL synthesiser (U10) is used in the TX module, this fractional-N synthesiser provides
very fine frequency resolution which enables the PLL used as a FM modulator by modulating the
PLL data. The modulation data is provided by DSP via the serial bus. The phase detector output
(charge pump) signal of U10 is smoothed and filtered by the loop filter to form the tuning voltage
for the VCO circuit.
The Power Amplifier (PA)